RELOCATION ASSISTANCE: Relocation assistance may be available
CLEARANCE REQUIRED FOR START: No
CLEARANCE TYPE: Secret
TRAVEL: Yes, 10% of the Time
DescriptionWe are seeking a front-end ASIC design engineer for architecture, design, and verification of full-custom digital and mixed-signal superconducting circuits. Must be proficient in Verilog, System Verilog or VHDL RTL coding, writing functional test benches, and have a thorough understanding of synchronous digital design concepts. Must be able to create a functional verification plan based on requirements of the circuit. Able to generate manufacturing test vectors and manufacturing test plan. Must be knowledgeable in synthesis, SDC constraints, formal verification, and static timing. Knowledge of scan insertion and ATPG is a plus. Able to interface with place and route engineers for floor planning and clock tree constraints and timing closure. Understanding of power estimation techniques is a plus. Automated place-and-route and physical verification knowledge is a plus. Must have strong written and oral communication skills.
Roles and Responsibilities: - Circuit behavioral coding in Verilog, System Verilog or VHDL RTL
- Circuit synthesis, formal verification, and static timing using state-of-the-art digital ASIC design tools
- Developing verification plans based on requirements of the circuit and creating circuit functional test benches in RTL
- Power estimation for superconducting circuits
- Generating manufacturing test vectors and manufacturing circuit test plan
- Assisting with the development of automated procedures to streamline digital design work flows
This position is contingent upon the ability to obtain/maintain an activeU.S. Government Secret ClearanceBasic Qualifications:
- Bachelor's degree with 5 years of experience, master's degree with 3 years of experience or Ph.D. with 1 year of experience in Science, Technology, Engineering, Mathematics, or related technical fields; an additional 4 years of experience may be considered in lieu of a degree.
- U.S Citizenship is required.
- Ability to obtain/maintain an active U.S. Government Secret Clearance
- Experience with full product life cycle (requirements, design, implementation, test) of ASIC designs and architecture
- Working knowledge of the front-end ASIC design flow from RTL to gates (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion)
- Experience with with current ASIC design tools for all phases described below: Simulation - Mentor ModelSim, Cadence Xcelium, Incisive or Synopsys VCS - Synthesis - Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler - Static Timing - Synopsys Primetime or Cadence Tempus
Preferred Qualifications:- Advanced degree - either MS or PhD
- Current security clearance or eligibility
- Knowledge of principles of superconductivity
- Experience with chip level integration and ASIC chip lead - Strong design automation skills
- Experience in CAD design network, tool configuration, and data management
- Familiarity with custom layout in Virtuoso, and physical verification (LVS/DRC) in Assura or Calibre. Familiarity with revision control and EDA standard formats used in cell/library development and modeling - Liberty (timing model), SDC (Synopsys Design Constraints)
Northrop Grumman provides a comprehensive benefits package and a work environment which encourages your growth and supports the mutual success of our people and our company. Northrop Grumman benefits give you the flexibility and control to choose the benefits that make the most sense for you and your family.
Your benefits will include the following: Health Plan, Savings Plan, Paid Time Off and Additional Benefits including Education Assistance, Training and Development, 9/80 Work Schedule (where available), and much more!
Primary Level Salary Range: $119,600.00 - $179,400.00
The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions.
Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.
The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates.
