Principal Digital Design Engineer / Chip LeadAbout the RoleAt Micron, we transform how the world uses information to enrich life for all. As a
global leader in memory and storage innovation, we develop technologies that accelerate
intelligence and enable the next era of AI, ML, and advanced computing.
Micron's Interface Pathfinding team operates at the leading edge of that mission -
driving performance-scaling innovation across circuits, signaling, packaging, and
interconnects with a 3-5 year technology horizon. A core part of that work is
silicon-based validation of novel PHY solutions, and we are building the team to
execute it.
As the
Digital Design Engineer / Chip Lead, you will be the technical anchor of a
deliberately small, senior team whose collective experience spans world-class analog
and digital design, decades of hands-on layout, silicon characterization, and physical design and design verification - united around the goal of carrying high-speed interface innovations from architecture to tape-out.
What You'll Own- Chip Architecture & Integration: Define top-level chip architecture, partition responsibilities across hard and soft IP blocks, and own the integration of hard macros alongside third-party soft IP.
- RTL Design: Author, review, and maintain synthesizable RTL (SystemVerilog) for all soft IP control blocks, CSR/register file, clocking control logic, and top-level integration.
- Timing Closure Leadership: Develop and own chip-level timing constraints (SDC), define clock domain crossing strategy, and provide timing budgets per block to the Physical Design engineer.
- Synthesis: Drive logic synthesis (DC / Genus) and guide optimization for PPA targets across all design blocks.
- Verification Coordination: Partner with DV staff to apply assertion-based verification, coverage-driven verification, formal methods and constrained-random techniques to ensure high quality verification of control logic, interfaces, and system behaviors.
- IP Management: Define interfaces between PHY hard macro, third-party soft IP, and internally designed blocks; manage IP integration agreements and vendor coordination.
- Tape-Out Ownership: Own and drive the tape-out checklist sign-off process, coordinating across Physical Design, Verification, and analog team members to achieve clean handoff to the foundry.
- Design Documentation: Author architecture specifications, block-level design specifications, and interface control documents that serve as the authoritative reference for the team.
- Follow-On Roadmap: Capture design decisions, lessons learned, and architectural rationale to accelerate follow-on chip development.
What You BringRequired- BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field
- 10+ years of ASIC/digital design experience with at least one prior tape-out in a chip lead, design lead, or senior designer role
- Expert-level proficiency in SystemVerilog RTL design and coding best practices
- Strong experience with logic synthesis tools (Synopsys Design Compiler or Cadence Genus) and static timing analysis (PrimeTime or Tempus)
- Proficiency with industry-standard RTL simulation and debug tools (VCS, Xcelium, or equivalent; Verdi or DVE for waveform debug)
- Solid understanding of CDC analysis methodologies and tools (SpyGlass, JasperGold CDC, or equivalent)
- Demonstrated experience integrating hard and soft IP blocks in a mixed-signal or PHY-adjacent chip environment
- Ability to work effectively as a technical lead on a small team - comfortable making decisions with incomplete information and owning the outcomes
- Strong written communication skills - this role produces specifications, not just code
- Experience partnering with design verification teams to define verification plans, review coverage metrics, and drive closure of functional and corner-cases prior to tape-out.
- It is expected that the candidate will be proficient in leveraging AI for productivity.
Preferred- Experience with high-speed PHY architectures (SerDes, DDR, or equivalent analog I/O structures)
- Familiarity with I2C management bus architecture, Eye Monitor control logic, or PRBS-based error counting implementations
- Experience with DFT strategy definition including scan insertion, ATPG planning, and boundary scan for high-speed I/O
- Familiarity with OTP/fuse-based trim and calibration architectures for PHY analog parameters
- Prior experience in a small team or startup-like environment where role boundaries are defined by need rather than org chart
Why This Role- You will have full technical ownership of a chip from day one - no waiting for a senior engineer to hand you a subsystem.
- You will work alongside genuinely exceptional analog designers - including engineers with deep SerDes and clocking expertise - in an environment where analog and digital engineers work as genuine collaborators, not in silos.
- The team is intentionally small and senior - decisions get made quickly, bureaucracy is minimal, and your judgment will be trusted.
- You are joining an active program with real momentum - your technical leadership will directly shape its trajectory and scope going forward.
A Note to All CandidatesThese roles are part of a deliberate effort to build a long-term, high-caliber team around a compelling PHY technology program. We are looking for engineers who want to
own something, build something, and grow with a program. If that description resonates, we'd like to hear from you.
