Job Responsibility
Palladium and Protium are high-capacitive, high-performance hardware assisted verification for complexed System-On-Chip (SOC). This role is to implement, verify, timing closure to tape out Palladium and Protium SOCs.
- Lead a team to implement SOCs or sub system chips
- Work on RTL synthesis and floor planning
- Build clock trees and perform optimizations
- Close timing, IR drop and physical verification
- Review and Document designs for taping out
- Interface with Front End RTL design teams and Back End Verification teams
Position Requirements/Qualifications:
- BS degree in Electrical Engineering with a minimum of 7 years of experience OR MS with a minimum of 5 years of experience OR PhD with a minimum 1 years of experience
- Experience with Cadence tools such as Innovus, Tempus, QRC, Voltus and Pegasus
- Experience with advanced technologies like 5nm, 3ns and 2nm nodes
- Experience using Linux servers, Script development using Shell/Perl/TCL
- Detailed knowledge about industry standard interfaces such as PCI Express, DDR, LPDDR, SRAM, UCIe, etc.
The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
