As a Principal Analog Design Engineer, you will be at the forefront of developing custom and original analog circuits. This is not integration or maintenance work, but an ambitious opportunity to contribute to world-class clocking, transmitter, and receiver circuits. You will own the complete lifecycle of building, from specifications through to post-silicon characterization. Responsibilities: • Lead the development of specialized analog components, focusing primarily on clocking (PLL, DLL, CDR) and transmitter/receiver circuits. • Contribute to the top-level PHY analog architecture decisions, including clocking topology and signal chain partitioning. • Build and maintain transistor-level simulation testbenches; perform process corner, statistical sampling, and evaluate variations to characterize build margin and yield sensitivity. • Define and detail clear interface specifications between custom analog blocks and the digital control wrapper. • Collaborate closely with the layout team to guide custom analog layout and support post-silicon characterization in the lab. Minimum Qualifications: • BS, MS, or PhD in Electrical Engineering or related field, or equivalent experience. • 10+ years of analog/mixed-signal IC build experience with at least one tape-out in a primary circuit ownership role. • Deep expertise in clocking circuit building - PLL, DLL, or CDR architecture and transistor-level implementation in sophisticated CMOS nodes. • Strong transistor-level simulation skills using HSpice or equivalent; comfort with corner, Monte Carlo, and mismatch analysis for yield-aware development. • Proven understanding of jitter analysis and its impact on high-speed link timing margins. • Ability to use AI/ML/LLMs for productivity and efficiency Preferred Qualifications: • Experience with high-speed transmitter development - output driver architectures, pre-emphasis, swing control, and impedance matching for multi-Gbps die-to-die or SerDes interfaces. • Background in rapid receiver development - sense amplifiers, CTLE/DFE equalization, sampler development, and threshold calibration. • Familiarity with die-to-die or chip-to-chip PHY architectures - UCIe, AIB, BoW, or proprietary short-reach interconnect standards. • Experience working with OTP/fuse-based calibration architectures and analog trim loop implementation. • Post-silicon characterization experience - correlating simulation results to measured eye diagrams, BER curves, phase noise plots, and jitter histograms on real hardware.