Job Title: Power Analysis

City: Mountain View

State/Province: California

Posting Start Date: 7/8/26

Job Description:

Job Description

Please look for engineers with power analysis experience
Verification engineers with power aware verification or low power design verification experience.
ASIC/SOC power engineers with experience on tools like PTPX / RTL-A.
• We are seeking a highly skilled and motivated Worker with expertise in power profiling and automation. The ideal candidate will play a crucial role in the analysis of power consumption, identifying hardware events that correlate with power consumption. Candidates will build run-time power models using Machine Learning techniques.
Key Responsibilities:
• RTL Design and Verification: Run power tests on RTL designs and verify that the test behavior matches the intent.
• Power Profiling: Utilize tools such as PPRTL or PTPX to perform comprehensive power profiling of hardware designs, identifying power-intensive areas and opportunities for optimization. Correlate various hardware events/telemetry with power profiles to understand power consumption.
• Data Processing and Automation: Develop and implement basic Python and/or TCL scripts for automation, data extraction, and processing of large volumes of hardware design data.
• Analysis and Reporting: Analyze profiling data, generate reports, and present findings to the design team, offering insights and recommendations for power reduction.
• Collaboration: Work closely with architects and designers to understand the power profile of the IP block and build a runtime power model using ML techniques.
Required Qualifications:
• Strong background in RTL design and verification principles.
• Demonstrable experience with power profiling tools such as PPRTL or PTPX.
• Proficiency in scripting languages like Python and/or TCL for automation and data manipulation.
• Ability to process and analyze large datasets related to hardware design.
Preferred Qualifications:
• Familiarity with machine learning models and their application in hardware design optimization is a plus.

Mandatory Skills: VLSI Physical Place and Route.

Experience: 5-8 Years.

The expected compensation for this role ranges from $60,000 to $148,500 .

Final compensation will depend on various factors, including your geographical location, minimum wage obligations, skills, and relevant experience. Based on the position, the role is also eligible for Wipro's standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), other paid and unpaid leave options.

Applicants are advised that employment in some roles may be conditioned on successful completion of a post-offer drug screening, subject to applicable state law.