Job Area:Engineering Group, Engineering Group > ASICS Engineering
General Summary:Work on activities related to Synthesis. structured placement, clock tree synthesis (CTS) and overall physical design convergence deliverables include custom design to drive higher performance with overall power containment. .
Responsibilities- Update the physical implementation flows for optimum PPA (power, performance, and area)
- Drive the development of semi-custom design techniques where appropriate to maximize utilization, performance, and power efficiency
- Use and extend/enhance design methodologies to achieve the best PPA through scripting
- Work independently with little supervision in collaboration between physical design and logic teams
- Use verbal and written communication skills to convey complex and/or detailed information to multiple individuals/audiences with differing knowledge levels. May require strong negotiation and influence, communication to large groups or high-level constituents
- Have a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to provide input on key decisions)
- Complete tasks that do not have defined steps; simultaneous use of multiple mental abilities is generally required to determine the best approach; mistakes may result in significant rework
- Exercise substantial creativity to innovate new processes, procedures, or work products within guidelines or to achieve established objectives
- Use deductive and inductive problem solving; multiple approaches may be taken/necessary to solve the problem; often information is missing or conflicting; advanced data analysis and interpretation skills are required
- Use tools/applications (i.e. Fusion Compiler etc.) to execute advanced architecture and design of multiple complex blocks and makes suggestions for design protocol
- Run advanced power checks on multiple blocks to ensure design specifications are met; makes recommendations to leadership when specifications are not met
Qualifications:- Bachelor's degree in Science, Engineering, or related field.
- 12+ years ASIC Physical design, Synthesis or related work experience
- Strong proficiency in P&R, timing analysis, CAD tools (e.g., Synopsys FC/DC, ICC2 or Cadence Genus, Innovus)
- Very good understanding of Logic optimization to drive high-speed design implementation, clock structures and power optimization
Preferred Qualifications- Bachelor's degree in Electrical Engineering, Computer Science, or Computer Engineering.
- 15+ years CPU or GPU design or related work experience.
- 10+ years of experience with architecture and design tools.
- 10+ years of experience with scripting tools and programming languages
Minimum Qualifications:• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Pay range and Other Compensation & Benefits: $164,000.00 - $246,000.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
