Semtech

Photo Engineer - Lithography & Mask Layout

Semtech$73K — $110K *
Manufacturing & Automotive
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • Bachelor's degree in Electrical Engineering, Materials Science, Physics, Chemical Engineering, or related field required
  • 5+ years of semiconductor photolithography experience, specifically with mask or reticle layout design
  • Hands-on experience with lithography steppers and coat/develop track systems in a wafer fab
  • Proficient in preparing and reviewing mask layout data (GDS, layer definitions, alignment strategies)
  • Strong understanding of photoresist processes and overlay metrology
  • Experience with SPC methodologies and data-driven process control

Responsibilities

  • Own photolithography processes for InP-based wafer fabrication
  • Develop and maintain photoresist and exposure processes
  • Provide troubleshooting support for lithography-related issues
  • Lead mask and reticle layout design for lithography layers
  • Define layout strategies and ensure manufacturability
  • Manage lithography equipment tools and performance monitoring
  • Drive yield improvement initiatives and analyze yield loss mechanisms

Benefits

  • Opportunity for hands-on technical ownership
  • Collaborative cross-functional work environment
  • Engagement in innovative photonic device manufacturing
  • Potential for career growth in advanced semiconductor technologies
  • Onsite role fostering direct communication and team dynamics
Full Job Description
Location: Alhambra, CA (Onsite)

Position Summary: The Photo Engineer - Lithography & Mask Layout position is a technical ownership role within an Indium Phosphide (InP) wafer fabrication facility supporting the manufacturing of DFB lasers, Semiconductor Optical Amplifiers (SOAs), and Gain Chip (GC) products. This role is responsible for end-to-end photolithography process development and manufacturing support, including full ownership of mask and reticle layout strategy, stepper and coat/develop track processes, and critical dimension (CD) and overlay control. The position serves as the primary lithography technical authority for InP device manufacturing, ensuring robust, repeatable, and high-yield lithography processes from tape-out through production. The role requires hands-on expertise in photolithography equipment, layout data preparation, process control, and yield improvement in a compound semiconductor wafer fab environment.

Responsibilities:

Photolithography Process Ownership and Manufacturing Support:

  • Own end-to-end photolithography processes for InP-based wafer fabrication, including DFB lasers, SOAs, and gain chip products


  • Develop, qualify, and maintain photoresist, exposure, develop, and post-lithography processes for front-end and back-end layers


  • Provide day-to-day manufacturing support, troubleshooting lithography-related issues and responding to process excursions


  • Support new product introduction (NPI), process transfers, and technology changes within the InP wafer fab


Mask and Reticle Layout Ownership:

  • Lead mask and reticle layout design for all lithography layers, including:


  • Layer definition, tone selection, and biasing strategy


  • Alignment mark strategy and overlay scheme definition


  • Reticle floor planning and field layout considerations


  • Serve as the primary technical owner for mask/reticle tape-out, review, release, and revision control


  • Coordinate directly with design teams and mask vendors on layout rules, data preparation (GDS, layer mapping), and mask re-manufacture activities


  • Ensure layout-for-manufacturability and lithography robustness across all device layers


Lithography Equipment and Process Control Ownership:

  • Own stepper and coat/develop track tools, including process qualification, recipe management, and performance monitoring


  • Define and maintain process control monitors (PCM/TCM) to ensure lithography process stability


  • Drive CD and overlay performance through SPC, process window characterization, and data-driven root-cause analysis


  • Partner with metrology and yield teams to improve lithography capability and reduce variability


Yield Improvement and Defect Reduction:

  • Lead lithography-related yield improvement initiatives and defect reduction efforts


  • Analyze lithography-related yield loss mechanisms and implement corrective actions


  • Support cross-functional yield reviews and excursion investigations


Documentation, Compliance, and Cross-Functional Collaboration:

  • Develop and maintain lithography process documentation, SOPs, travelers, and control plans


  • Ensure compliance with internal manufacturing standards and quality systems


  • Work cross-functionally with design, process, equipment, and manufacturing teams to support production goals


Minimum Qualifications:

  • Bachelor's degree or higher in Electrical Engineering, Materials Science, Physics, Chemical Engineering, or a related field required


  • Minimum of 5+ years of experience in semiconductor photolithography, with direct involvement in mask or reticle layout design


  • Hands-on experience with lithography steppers/aligners and coat/develop track systems in a wafer fab environment


  • Experience preparing, reviewing, and releasing mask layout data (GDS, layer definitions, alignment strategies)


  • Strong understanding of photoresist processes, CD control, overlay metrology, and alignment schemes


  • Familiarity with SPC and data-driven process control methodologies


  • Experience interfacing with mask vendors and managing mask lifecycle activities


  • Preferred experience in InP or III-V compound semiconductor wafer fabrication


  • Familiarity with DFB lasers, photonic integrated circuits (PICs), or optical device manufacturing preferred


  • Experience supporting high-mix, low-volume manufacturing environments preferred


  • Knowledge of mask fabrication processes and mask-related yield risks preferred


The intent of this job description is to describe the major duties and responsibilities performed by incumbents of this job. Incumbents may be required to perform job-related tasks other than those specifically included in this description.

A reasonable estimate of the pay range for this position is $73,000 - $110,000. There are several factors taken into consideration in determining base salary, including but not limited to: job-related qualifications, skills, education and experience, as well as job location and the value of other elements of an employee's total compensation package.

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About Semtech

Semtech Corporation is a leading supplier of high-performance analog and mixed-signal semiconductors and advanced algorithms. The company is dedicated to providing proprietary solutions and breakthrough technology for circuit protection (TVS), high-reliability power management, and advanced communications technologies. Semtech's products are used in some of the most innovative systems and products in the fastest-growing markets in technology today, including the Internet of Things (IoT), data centers, and mobility. Semtech is publicly traded on the NASDAQ under the symbol SMTC.
Learn more about Semtech
Size
1,439 employees
Market Cap
$1.7 billion
Industry
Net Income
$39.8 million
Founded
1960
5 Year Trend
+6.4%
Revenue
$568.4 million
NASDAQ

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