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X In most instances, this position requires in-person interviews as part of the hiring process.Note: By applying to this position you will have an opportunity to share your preferred working location from the following:
San Diego, CA, USA; Mountain View, CA, USA.
Minimum qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience verifying digital logic at RTL using SystemVerilog for ASICs.
- 4 years of experience in people management, developing employees.
- Experience constructing reusable verification components and environments using UVM.
- Experience leading fully functional verification and performance validation cycle of subsystems such as: Camera ML/Multimedia - ISP, Display, TPU/GPU, processors, or at the SOC level.
Preferred qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with Camera ISP image processing or other Multimedia IPs such as Display or Video Codec or ML Accelerator verification.
- Experience with System Verilog Assertions (SVA), assertion-based verification, and formal verification.
- Experience working with software teams to define hardware/software interfacing including control/status registers, security, and error handling.
- Experience with Low Power Verification and power management flows.
Responsibilities - Plan and execute IP- and subsystem-level verification for complex ISP/Multimedia hardware, partnering with architecture and design teams to identify critical scenarios and support full-chip integration.
- Lead subsystem verification for power and performance, including low-power design, embedded processor integration, and DVFS features.
- Build and enhance SystemVerilog/UVM constrained-random testbenches, debugging failures alongside designers to ensure functionally robust blocks.
- Define, measure, and close comprehensive coverage across stimulus and corner cases to eliminate verification holes and drive progress toward tape-out.
- Manage and mentor a global DV team across methodology, scheduling, regressions, and reviews, while aligning with SoC teams to track all milestone deliverables.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $278000 (USD) 20% bonus target equity benefits
Learn more about benefits at Google .
