MTS, DDR Design Verification (AI2487)

SiMa Technologies

$176K — $281K *
Information Technology
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • BS in Computer Science/EE with 10+ years or MS with 8+ years in SoC design verification
  • Experience with block, cluster, or chip/SoC level verification
  • Proficiency in System Verilog, UVM, and coverage-driven methodologies
  • Must have DDR controller or DDR-IO verification experience
  • Strong understanding of LPDDR JDEC specifications, particularly LPDDR5
  • Familiarity with DDR controller and PHY functionality
  • Experience developing test bench components and test plans for DDR/LPDDR IP verification

Responsibilities

  • Define and develop verification methodology for SiMa.ai's MLSoC™
  • Create DDR test plans, test benches, and test cases
  • Execute test plans to verify MLSoC - DDR functionality
  • Conduct performance and coverage analysis
  • Collaborate closely with the Architecture, RTL/uArch, and cross-functional teams
  • Participate in DDR bring up on MLSoC Silicon in the lab

Benefits

  • Opportunity to work in an innovative technology environment
  • Collaborative work with cross-functional teams
  • Hands-on experience with cutting-edge silicon testing
  • Full-time onsite role fostering team engagement
  • Equal opportunity employer committed to diverse hiring practices
Full Job Description
Description

Job Title: MTS, DDR Design Verification

Job Location: San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office)

Job ID: AI2487

Job Description:

As the DDR Design Verification Engineer, you will participate in definition and develop the verification methodology for SiMa.ai's MLSoC™. You will be responsible for developing DDR test plans, test-benches (drivers, monitors and checkers/scoreboard etc..) and test cases. You will be executing test plans to verify the MLSoC - DDR functionality, performance and coverage analysis. You will work closely with the Architecture, RTL/uArch, and cross-functional teams. Opportunity to participate on DDR bring up on MLSoC Silicon in the lab.

Required Background:
  • BS in Computer Science/EE with 10+ years of experience or MS in computer science/EE with 8+ years of experience in SoC design verification.
  • Experience with block level, cluster level or chip/SoC level verification.
  • Proficiency in system verilog, UVM, constrained random and coverage driven verification methodology.
  • DDR controller and/or DDR-IO verification experience is a must.
  • Very good understanding of LPDDR JDEC specifications preferably for LPDDR5.
  • Good understanding of DDR controller and phy functionality.
  • Experience with development of test bench components, test plans for DDR/LPDDR IP verification.
  • Good system verilog programming, debug and problem solving skills.
  • Scripting languages, python or perl is a plus.


Personal attributes:

Can-do attitude. Strong team player. Curious, creative and good at solving problems. Execution and results-oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.

The annual salary for this position ranges from $176,200 to $281,900. The actual annual salary offered will depend on several factors, including - among others - job-related skills, experience, technical expertise, qualifications, work location, and business needs. The annual salary range for this position is subject to change and may be adjusted in the future.

In addition to base salary, this role is also eligible for private company equity, and a comprehensive package of employee benefits. Please note that the salary ranges listed for U.S. roles reflect base salary only and do not include equity or other forms of compensation.

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