As a Senior Engineer, Principal Engineer, or Member of Technical Staff, Design Architect in the Next-generation HBM Architecture Team, you will design, simulate, analyze, and optimize the architecture of 3D-stacked, high-performance memories. Apply your knowledge to explore trade-offs in 3D-stacked logic and memory designs in close collaboration with peer architecture and design teams. Your responsibilities will include definition of, evaluation of, and specification of circuit implementations, technology requirements, thermal performance improvements, power delivery architectures, and on- and off-chip interfaces.
Responsibilities:- Design, optimize, and simulate critical analog and/or mixed-signal circuits.
- Architect and design power delivery for high-performance, stacked memories.
- Analyze, specify, and prototype on-/off-chip interfaces.
- Perform timing, area, power, and complexity analysis for high-performance, low-power circuits.
- Define architectures for improved thermal management.
- Conduct pathfinding activities for future-generation stacked-memory products.
- Compose and maintain clear architecture documentation.
Minimum Qualifications:- Experience with analog and/or mixed-signal design, including simulation and floorplanning.
- Experience with transistor-level simulation (e.g., FineSim, HSPICE) including corner analysis.
- Ability to analyze architecture tradeoffs and use findings to develop specifications.
- Experience with power delivery analysis, tradeoffs, constraints, and challenges.
Preferred Qualifications:- Familiarity with DRAM or high-performance, 3D-stacked memory devices like HBM.
- Contributions to thermal and/or power delivery solutions for stacked architectures.
- Experience in one or more scripting languages (e.g., Python, Perl) and hardware description language (e.g., Verilog).
- A Masters or PhD in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience.
- 5+ years of proven experience delivering mixed-signal circuit designs, 3D-stacked memory or logic designs, or complex packaging architectures.
The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$146,000.00 - $297,000.00 a year
Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
To learn more about Micron, please visit micron.com/careers
