Note:

This role requires regular onsite presence to fulfill essential job responsibilities.

• Defines electrical validation strategy for memory IO interfaces to achieve optimized electrical performance and meet product production goals.
• Validates circuit analog performance, electrical signal integrity compliance to industry standard specifications, and system level margin for stable operation and production target prediction.
• Defines MRC (Memory Reference Code) requirements for validation and margin optimization and analyzes, validates, debugs, and optimizes MRC steps and values to optimize margins and quality.
• Conducts and participates in multidisciplinary research in the design, development, testing, validation, and utilization of memory IO and mixed signal architectures inclusive of industry standard datacom applications and custom Intel interfaces.
• Develops procedures, analysis, and designs for validation, validation infrastructure, and systems margin validation.
• Analyzes internal and external customer returns with emphasis on improving yields and driving test escape closure.
• Applies and uses independent evaluation to select components and equipment based on analysis of specifications, performance, and reliability.
• Performs debug to identify root causes and resolves all functional and triage failures for electrical issues.
• Tests interactions between various electrical design features using validation infrastructure.
• Applies understanding of DFT and DFM to collaborate with architecture, design, and presilicon verification teams to ensure capability to validate and test IO architecture implementations.
• Prepares validation specifications, evaluates IP, and generates test reports. Ensures products conform to standards and specifications.

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.

Minimum Qualifications:

• Bachelors or Master's degree in electrical engineering or physics or computer engineering or another relevant field
• 5+ years of experience in Memory/DDR technology
• 5+ years of hands-on validation and debug experience at system level and memory interfaces
• 5+ years of experience with industry-standard JEDEC memory protocols and test methodologies

Preferred Experience:

• Understanding platform level signal integrity and power integrity technologies a definite asset
• Experience with validation of high-speed I/O interfaces, including understanding of Tx, Rx, PLL, DLL, Clocking, and Equalization
• Knowledge of computer architecture (CPU, DDR Memory technologies) and software/firmware architecture (bios, firmware debug experience)
• Hands-on experience of validation & debug using tools such as Oscilloscopes, Signal generators, BERT, and Logic analyzers
• Familiarity of Server/Xeon Memory RAS features
• Python scripting/programming skills
• Must be a self-starter and be able to independently drive tasks to completion
• In-depth knowledge of DRAM, Memory Controller and DDRIO/PHY architectures and design/validation concepts
• Familiarity with Memory Reference Code (MRC), DDR training algorithms
• Working knowledge of high-speed analog and digital circuits of IO

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Work Model for this Role

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