Job Description:The Networking Connectivity Solutions team is looking for a highly skilled Lead Layout Designer II that can contribute to the layout and physical verification of high frequency (up to 10Gbps) physical layer interfaces for USB and Ethernet based standards. The candidate should be a self-driven individual who is capable and excited to learn about new technologies. This position is at Microchip Technology Inc. located in Chandler, Arizona.
Job responsibilities and duties include:
- Block and cell development including floor-planning, layout creation and optimization
- Perform custom layout design using analog layout techniques
- Perform physical verification and electromigration check
- Work directly with Design Engineering to release custom designs to stream out
- Operate effectively in a team environment while contributing to the team's success
- Experienced self-driven individual who is capable of working at a high level with minimal direct supervision.
Requirements/Qualifications:- Education: (Engineering/Technology/Technical School) with 7+ years' experience in custom analog CMOS layout design
- Experience with Cadence, Pegasus and Calibre EDA tools
- Knowledge of Advanced CMOS process and Foundry Design rules, including geometries 28nm and below
- Strong problem-solving skills and significant experience in physical verification
- Programming skills with Cadence SKILL is preferred, but not required
- High level of attention to detail
- Excellent technical, verbal, and interpersonal skills
- Ability and willingness to work on multiple projects and technologies at any given time
Travel Time:0% - 25%
Physical Attributes:Feeling, Hearing, Seeing, Talking, Works Alone, Works Around Others
Physical Requirements:90% Sitting, 10% Standing/Walking
