About the role:As the Lead Hardware System Architect, you will own the end-to-end hardware development lifecycle for our next-generation graphics compute platforms, high-performance GPU servers, and ultra-high-speed PCIe graphics form factors. You will act as the technical bridge between advanced graphics silicon packaging and system-level deployment, driving physical architecture, functional partitioning, and high-speed fabric optimization for massive graphics workloads and real-time rendering infrastructure.
In this role, you will not just oversee board layouts; you will define the physical topologies that enable cutting-edge graphics compute scaling. You will serve as the ultimate technical escalation point for our global JDM/ODM engineering partners, steering them through complex bring-up, signal integrity boundaries, and root-cause failure analysis to deliver flawless graphics hardware on schedule.
This role is on-site, 5 days a week.What you'll do:1. Physical System Architecture & High-Performance Graphics Design- Architect the Platform: Drive system-level architectural trade-offs, balancing high-performance GPU silicon package constraints, high-speed routing density, thermal mechanics, and ultra-high-density power delivery networks (PDNs).
- Own High-Speed Topologies: Design and optimize complex PCB topologies utilizing PCIe Gen 5/Gen 6 (CEM specifications) and proprietary/consortium scale-up interconnect fabrics designed for parallel compute and graphics scaling (e.g., NVLink, Infinity Fabric, UA Link).
- Systemic Co-Design: Collaborate with Silicon, Signal/Power Integrity (SI/PI), and Thermal/Mechanical teams to define robust board stack-ups, low-loss material selection, and multi-phase power zones handling massive transient loads from modern graphics processors.
- Management Integration: Ensure seamless integration of out-of-band telemetry and management infrastructure, designing physical routing for Baseboard Management Controllers (BMCs), SPI, and I2C/SMBus topologies.
2. Technical JDM/ODM & Supplier Governance- Lead Technical Enablement: Serve as the primary technical authority interfacing with international JDM/ODM layout and hardware engineering teams.
- Triage & Failure Analysis: Lead complex hardware debug, component-level troubleshooting, and failure analysis (FA) during early-phase platform bring-up and validation of graphics compute hardware.
- DFX & Execution Governance: Enforce rigorous design reviews and strict compliance with DFX (Manufacturing, Assembly, Test, and Automation) standards to ensure high-yield transitions from EVT/DVT to High-Volume Manufacturing (HVM).
Qualifications:- Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
- Experience: 8+ years of hardware design experience, with a proven track record of shipping high-performance graphics hardware, GPU motherboards, or high-density parallel compute accelerator boards.
- Fabric & Bus Expertise: Deep, hands-on experience designing with PCIe Gen 5/6 and high-speed serdes (112G/224G PAM4 architectures). Familiarity with CXL or scalable interconnect fabrics is highly desired.
- Advanced Power & SI/PI: Strong understanding of high-frequency PCB layout constraints, via optimization, and power delivery networks capable of handling extreme di/dt step loads inherent to dynamic graphics workloads.
- Hardware Tooling: Proficiency with advanced EDA tools (e.g., Cadence Allegro, OrCAD) and familiarity with simulation tools for validating physical design assumptions.
- Global Vendor Triage: Experience directing overseas ODM engineering teams through architectural definition, layout execution, and laboratory hardware triage.
Preferred Qualifications- Direct experience with Open Compute Project (OCP) standards or industry-standard multi-GPU form factors.
- Familiarity with liquid cooling or advanced phase-change thermal infrastructure and its unique spatial and material constraints on physical board design.
- Hands-on lab experience utilizing high-speed validation equipment (e.g., oscilloscopes, VNAs, BERTs) for signal and power verification on graphics hardware.
Compensation Range: $200,000-$250,000 per year (California). This range represents the anticipated base pay for this role; the final offer may vary based on qualifications, experience, and location.
This role is onsite - 5 days a week.Benefits:- Medical, Dental, & Vision - 100% covered premiums
- Equity - Stock Options
- 401(k) match
- WFH Equipment Reimbursement
