Job Requirements We are looking for a Senior Physical Design Engineer with 8-14 years of experience to lead and execute RTL to GDSII implementation for low power SoCs on advanced nodes. This role demands deep expertise in Synopsys Fusion Compiler, strong scripting and automation, and a proven track record of achieving best-in-class PPA.
What You will Do:- Drive physical design flow: synthesis, floorplanning, placement, CTS, routing, timing closure.
- Deliver low power designs using advanced UPF methodologies on 5nm/3nm nodes.
- Resolve SoC/SS integration challenges including SDC constraints and UPF promotion/pushdown.
- Develop and maintain automation flows using Tcl, Python, and Shell.
- Collaborate with cross-functional teams for design closure and signoff.
- Mentor and lead junior team members.
- Innovate and contribute to flow/methodology improvements.
What You Will Bring:- B.Tech/M.Tech in ECE, EE, or VLSI.
- 8-14 years hands-on physical design experience.
- Expert in Fusion Compiler, low power design, and PPA optimization.
- Strong scripting skills (Tcl/Python/Shell).
- Good understanding of SoC hierarchy, signoff flows, and constraint management.
- Excellent problem-solving, communication, and leadership skills.
Preferred:
Experience in top-level SoC integration, signoff tools (PT, ICV), and DFM check
Pay range:$130K- $140K
Compensation decisions are made based on factors including experience, skills, education, and other job-related factors, in accordance with our internal pay structure. We also offer a comprehensive benefits package, including health insurance, paid time off, and retirement plan.
Benefits Full-time (Regular)• 401(k)
• 401(k) matching
• Dental insurance
• Health insurance
• Life insurance
• Paid time off
• Referral program
• Vision insurance
• Short/Long Term Disability
