Job Title: Layout Engineer
Job Description: Coordinate design changes and design fitting issues, and other technical data to ensure customer's design can fit TSMC's production flow and procedures. Specific tasks will include but not limited to: Acting as liaison between customer and TSMC fab manufacturing staff; Providing training and on-site support to TSMC's US customers of TSMC specific advanced processing analog block layout; Utilizing knowledge of TSMC's design rules; and Implementing blocks of customer's chip, covering floor plan, timing and noise closure and power planning. Provide analog block layout floor-plan and layout guideline.
Requirements: Bachelor's degree or foreign equivalent in Electrical Engineering, Photonics and Optoelectronics, Computer Science or related field, and three (3) years of experience in a related position
Work experience or academic coursework must have included: Knowledge of chip implementation technology and semiconductor fabrication processes and procedures; knowledge in ANALOG layout skills, mixed-mode electronic circuits, and semiconductor device expertise; and Knowledge of layout tools such as VIRTUOSO as well as verification tools including Calibre
Work site: TSMC Technology, 2851 Junction Ave., San Jose, CA 95134 and various unanticipated work location
Salary Range: $120,182 to $167,000/year.
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Date: Jun 26, 2026
Country/Region: US
City: San Jose
Company: TSMC Technology, Inc.
