Job Title: Layout Engineer
Job Description: Coordinate the design changes, design fitting issues, and other technical data to ensure customers' designs can fit TSMC's production flow and procedures. Specific tasks include but are not limited to: Acting as liaison between customer and TSMC fab manufacturing staff; providing training and on-site support to TSMC's U.S. customers of TSMC specific advanced processing DDRIO/SerDes/RF layout, utilizing knowledge of TSMC's design rules; Implementing blocks of customer's chip, covering floor plan, timing and noise closure and power planning. Provided DDRIO/SerDes/RF block layout floorplan and layout guideline.
Requirements: Master's degree or foreign equivalent in Electrical Engineering, Photonics and Optoelectronics, or a related field of study, and two (2) years of experience in a related position
Work experience or academic coursework must have included: Knowledge of chip implementation technology and semiconductor fabrication processes and procedures; knowledge in DDR IO layout skills, mixed-mode electronic circuits, and semiconductor device expertise; and knowledge of layout tools such as VIRTUOSO as well as verification tools like Calibre
Work site: TSMC Technology, 2851 Junction Ave., San Jose, CA 95134 and various unanticipated work location
Salary Range: $120,182 to $160,000/year.
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Date: Jun 26, 2026
Country/Region: US
City: San Jose
Company: TSMC Technology, Inc.
