Job Details:Job Description:About the RoleJoin a team developing next-generation CPU cores that power client, server, IoT, and AI platforms. As a
Junior Senior Physical Design Engineer (CPU), you will contribute to cutting-edge silicon design using advanced process technologies. You will work alongside experienced engineers to support implementation from RTL to GDS, gaining hands-on experience in high-performance, power-efficient processor design.
What You'll DoKey responsibilities will include but not limited to: - Support physical design execution for CPU core or subsystem blocks under guidance
- Assist with synthesis, place and route (PnR), and physical verification tasks
- Perform analysis for timing, power, and design rule compliance
- Debug and resolve design issues with mentorship from senior engineers
- Contribute to script and flow development (e.g., TCL, Python)
- Collaborate with cross-functional teams including RTL design, verification, and full-chip integration
- Document design work and contribute to best practices and design flows
Behavioral traits that we are looking for: - Strong learning agility and curiosity
- Pays close attention to detail and quality
- Communicates clearly and effectively in a team environment
- Demonstrates adaptability and openness to feedback
- Builds collaborative relationships across teams
Qualifications:You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Note: For information on Intel's immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship InformationMinimum Qualifications and Experience:
Bachelors in Computer / Electrical Engineering or related field with 2+ years of educational or work experience. Or a Masters in the same field with 3+ months of educational experience.
Your experience described above must be in the following:
- Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure
- PV convergence (including static timing and power analysis)
- Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks.
- Scripting in an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby)
- Experience with one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP
Preferred Qualifications and Experience:- Physical design best known practices concerning floor-planning, routing techniques, clock distribution
- Static Timing Analysis, Noise analysis, and reliability verification techniques
- RTL to GDS methodologies and formal equivalence
- Familiar with Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus)
Job Type:College Grad
Shift:Shift 1 (United States of America)
Primary Location:US, Oregon, Hillsboro
Additional Locations:Work Model for this RoleThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
