Opportunity Overview

Teradyne's Compute Test Division develops advanced test solutions for next-generation silicon, including high-performance SoCs and accelerators powering modern compute and AI systems. We are seeking a Junior FPGA Engineer to support the design and delivery of high-performance FPGA-based solutions at the heart of our test platforms. This role offers the opportunity to grow at the intersection of FPGA design, board-level hardware, and system architecture while working alongside experienced engineers on high-speed interfaces, complex digital systems, and system-level constraints. Based on site in North Reading, Massachusetts, the position is expected to work in the office three days per week and collaborate across functions on solutions that directly affect the quality and performance of cutting-edge semiconductor devices.

• Support FPGA design implementation and bring-up under the guidance of senior engineers.
• Develop FPGA logic for defined interfaces and subsystems as part of a larger design.
• Collaborate with hardware, software, systems, and design verification teams on system-level solutions, simulations, and test coverage goals.
• Support timing closure, resource optimization, lab bring-up, debugging, and basic root cause analysis using JTAG and lab instrumentation.
• Build and maintain TCL and Python scripts that support design and validation workflows.
• Partner in code reviews, design discussions, and PCB and system design decisions that affect FPGA performance, building toward greater technical ownership over time.

All About You

We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you're ready to join us in this mission, take a closer look at the minimum criteria for the position.

• 2+ years of hands-on experience in FPGA design and development.
• Working knowledge of Verilog/SystemVerilog for design and debugging.
• Exposure to AMD (Xilinx) and/or Intel FPGA toolchains, including synthesis, implementation, and timing closure.
• Understanding of digital design fundamentals and the ability to interpret schematics.
• Some exposure to high-speed interfaces such as PCIe, DDR, SerDes, or similar technologies and familiarity with protocols such as AXI4, USB, I2C, and SPI.
• Basic experience bringing up or debugging FPGA designs on hardware platforms.
• Basic TCL and Python scripting skills and experience with version control systems.
• Strong communication and collaboration skills, with an interest in developing system-level thinking and the ability to debug across FPGA, board, and software boundaries.
• Preferred: coursework or project experience with SystemVerilog-based verification methodologies such as UVM; familiarity with FPGA SoCs and embedded processor subsystems; exposure to ATE or measurement equipment design; a basic understanding of signal integrity and high-speed serial interfaces; or familiarity with AI tools for engineering design.

We are only considering candidates local to the position location and are unable to provide relocation for this position.

This position is not eligible for visa sponsorship.

Compensation:

The base salary range for this role is $98,700 - $157,900. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance.

Benefits:

Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here to see details.

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