As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best-in-class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands-on role with opportunities to own blocks or top-level integration across multiple product generations. Key Responsibilities • Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. • Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. • Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY-adjacent logic) with focus on robust physical integration and timing/power integrity. • Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. • Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. • Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements. • Support tape-out execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis. • Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development. Required Qualifications • Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs. • Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent). • Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew, etc.). • Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications). • Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality. Preferred Qualifications • Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs. • Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field. • Minimum 10 years of experience in a related field. • Proven ability to mentor and develop engineers early in their careers.