General Summary:QCT mixed-signal IP design team is looking for skilled system architects to design high-speed, high-performance, and low-power HBM Phys. You'll help with system definition, architecture, and end-end design cycle - starting from early ideas all the way to final chip production and validation.
Responsibilities:
- Own the HBM PHY architecture and system definition, driving end-to-end solutions that meet performance, power, area, and reliability targets.
- Develop and manage system timing budgets across on-die, and off-chip interfaces, ensuring robust operation across all conditions.
- Lead cross-functional architectural trade-offs and execution, working closely with SoC, memory, package, and validation teams.
- Deliver best-in-class HBM PHY solutions through technical leadership, innovation, and alignment with product roadmap requirements.
Required for this Role:- 5+ years of experience in HBM PHY architecture and design for high-performance memory interfaces.
- Strong understanding of JEDEC memory standards (HBM, LPDDR, DDR) and their application to PHY architecture and design.
- Expertise in link budgeting, timing closure, margin analysis, and PHY training methodologies for high-speed interfaces.
- Proven ability to drive technical discussions and collaborate effectively across cross-functional and globally distributed teams.
Preferred Qualifications:- Familiarity with signal integrity (SI), power integrity (PI), package effects, and power delivery networks for high-speed memory systems.
- Knowledge of advanced process technologies, mixed-signal design principles, and high-speed interface implementation.
- Understanding of design-for-yield, manufacturability, and production challenges associated with high-speed memory links.
- Proficiency in Unix/Linux environments and scripting languages such as Perl, TCL, or Python for automation and analysis.
Keywords- HBM, DDR, DRAM, PHY, high-speed interface, signal integrity, power integrity.
Educational Requirements- Required: Bachelor's, Electrical Engineering
- Preferred: Master's, Electrical Engineering
Minimum Qualifications:• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Pay range and Other Compensation & Benefits: $164,000.00 - $246,000.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
