Opportunity Overview

Semiconductor test instruments span a deep vertical stack: application software on a host PC, an instrument driver and API layer, embedded software running on module-level processors, a hardware abstraction layer, FPGA logic, and finally the ASICs and DACs that put real volts and amps on a device under test.

Most engineers own one or two of those layers. This role owns the seams between all of them.

You will be the engineer who can start from "the test program asked for X and the pin did Y" and trace the full chain, including API call, driver layer, register write, FPGA logic, DAC code, and output voltage, until you isolate the layer where behavior diverges from intent. You will read code, RTL, and schematics beyond your own deliverables. You will find defects in a new board's software stack before the board arrives. And you will bring logic design, FPGA, and software engineering into the same conversation and keep them aligned until the issue is closed.

• Trace and root-cause defects end to end across the instrument stack, from host application and driver API through embedded software, the hardware abstraction layer, FPGA and ASIC/DAC programming, and drive the fix in whichever layer owns it.
• Own the correctness of translation layers, including API surfaces and enumerations, register maps, bitstream encodings, and calibration math that converts engineering units into DAC codes and back.
• Review code, HDL and schematics beyond your own deliverables, including abstraction-layer source, FPGA logic, register map changes across board revisions, and power-on versus runtime initialization paths.
• De-risk new board revisions before hardware arrives by reviewing initialization, connect/disconnect pathways, and break-before-make sequencing.
• Build and improve debug tooling, instrumentation, unified timeline views, automated analysis workflows, and AI-assisted debug and log review capabilities.
• Support internal diagnostic, calibration, continuity, and production verification paths alongside customer-facing APIs.
• Align logic design, FPGA, embedded software, and applications teams around shared failure models and maintain knowledge-sharing documentation.
• Work backward from customer use cases to verify end-to-end system behavior across the stack.
• Set technical direction for cross-layer debugging and participate in design, code, and RTL reviews.
• Partner with component and silicon vendors to resolve system-level integration issues.
• Mentor engineers and help expand cross-disciplinary debugging capabilities across the organization.

All About You

• Approximately 6+ years of engineering experience, including ownership across firmware and application software on at least one shipped product.
• Proficiency in C and/or C++ for embedded or Linux environments and Python for automation, tooling, and analysis.
• Strong register-level debugging skills with the ability to interpret datasheets, register maps, and DAC/ADC behavior.
• Demonstrated experience solving cross-layer system problems and driving root cause across organizational boundaries.
• Experience influencing teams outside your formal reporting structure.
• Ability to read schematics and understand analog intent, voltage ranges, current limits, protection mechanisms, and signal paths.
• Working knowledge of SPI, I²C, UART, PCIe, and Ethernet/UDP.
• Excellent written and verbal communication skills.
• BS or MS in Computer Engineering, Electrical Engineering, Computer Science, or equivalent experience spanning hardware and software.
• Curiosity and willingness to work outside of narrowly defined ownership boundaries.

• Firmware or board bring-up experience, including bootloaders, BSPs, or device drivers.
• Exposure to FPGA development flows and the ability to read HDL.
• Semiconductor test, instrumentation, measurement, or automation experience.
• Calibration systems and engineering-unit conversion experience.
• AI-assisted debugging, code review, or log analysis experience.
• Multi-processor embedded system experience.

We are only considering candidates local to position location and are unable to provide relocation for this position.

This position is not eligible for visa sponsorship.

Compensation: The base salary range for this role is $141,400 - $226,200. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance.

Benefits: Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here to see details.

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