Hardware Engineer

Keylent, Inc.

• $90K — $130K *
San Diego, CA 92154In-Person
Telecommunications & Hardware
5 - 7 years of experience
Reposted Today
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Job Overview by Ladders

Qualifications

  • 6+ years of experience in hardware/board design.
  • Proven experience with HDI/multi-layer moderate to complex SoCs.
  • Expertise in system architecture, including PDN design and SI/PI management.
  • Familiarity with embedded systems and basic board bring-up processes.
  • Knowledge of firmware and post-silicon validation for ARM-based SoCs.

Responsibilities

  • Collaborate with cross-functional teams to gather and analyze project requirements.
  • Lead the design of complex boards, defining power grids and overall system architecture.
  • Develop schematics and coordinate with PCB designers to drive the design process.
  • Conduct board bring-up and debugging activities in the field.
  • Utilize knowledge of SI/PI challenges to enhance board performance.

Benefits

  • Full-time employment status with a possibility of contract conversion.
  • Onsite work from Day 1 in a collaborative environment.
  • Opportunity to work with advanced technologies in a pivotal engineering role.
Full Job Description
Role: Hardware Engineer

Location: San Diego, CA

Duration: Full Time/Contract

Day 1 onsite

HW/architecture design side : one who can collate requirements and drive complex boards by defining power grid, system architecture and then preceding to schematics and ability to work with a PCB designer to drive the design, SI/PI etc.

- He/she should also be knowledgeable on board basic bring-up /debug in the field.

Requirements :

- 6+ years' experience

- Experience in HW/Board design with HDI /multi-layer moderate to complex SoCs. Ability to architect the board from specification, PDN design and knowledge of SI/PI challenges.

-Some experience/exposure to embedded systems/basic board bring-up, firmware and post silicon validation for ARM based SoCs.

- Ability to learn new technologies and tools including HSIO characterization for SoCs.
* Ladders Estimates

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