Teradyne

FPGA Engineering Manager (Nextest, Tualatin, OR)

Teradyne$171K — $273K *
Telecommunications & Hardware
11 - 15 years of experience
Job Overview by Ladders

Qualifications

  • B.S. or M.S. in Electrical Engineering or related field
  • 12+ years of experience in Digital ASIC or FPGA design
  • 5+ years as an FPGA/ASIC project lead
  • Extensive RTL coding experience (Verilog preferred)
  • Experience with digital simulation and static timing analysis tools
  • Familiarity with PCIe, DDR interfaces, and FPGA development tools (Vivado/Quartus)
  • Excellent communication and presentation skills

Responsibilities

  • Plan and manage multiple FPGA development projects
  • Represent the FPGA team at program reviews
  • Support sustaining issues
  • Collaborate with hardware, software, and firmware teams for integration
  • Recruit and retain a high-performing engineering team
  • Conduct performance evaluations for team members
  • Participate in FPGA design, including RTL coding and validation

Benefits

  • Robust medical, dental, and vision plans
  • Flexible Spending Accounts
  • Retirement savings plans
  • Life and disability insurance
  • Paid vacation and holidays
  • Tuition assistance programs
Full Job Description
Opportunity Overview

Teradyne's Memory Test Division (MTD) seeks a motivated and technically driven FPGA Manager to support the development of our growing portfolio of cutting-edge memory test solutions.

MTD creates advanced solutions for complex testing applications, driving innovation through creativity and diverse perspectives. Our test instrumentation supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery.

We are looking for a hands-on FPGA Engineering Manager to oversee the development of cutting-edge memory test solutions. This role combines technical oversight, project management and direct engineering contributions, ensuring the successful delivery of high-quality, reliable products that support the world's most advanced memory technologies.

Your key responsibilities as FPGA Engineering Manager will be:

  • Plan, prioritize, and manage multiple FPGA development projects, ensuring on-time delivery within budget and scope.
  • Represent the FPGA team on project core teams and at program reviews.
  • Provide support for sustaining issues.
  • Work closely with cross-functional teams, including hardware, software, and firmware engineers, to ensure seamless integration of FPGA designs into larger systems.
  • Recruit, onboard, and retain top engineering talent to build a high-performing team.
  • Set goals and conduct regular performance conversations for a team of 4 to 6 engineers.
  • Contribute to FPGA team process improvement initiatives.
  • Provide hands-on technical guidance to the FPGA engineering team, including reviewing and contributing to FPGA architectures, designs, and specifications.
  • Actively participate in FPGA design and development, including RTL coding, synthesis, timing closure, and lab validation.


All About YouWe seek individuals who share our passion. Our commitment to customer success drives us to go the extra mile. If you're ready to join us in this mission, take a closer look at the minimum criteria for the position.

  • B.S. or M.S. in Electrical Engineering or closely related discipline
  • 12+ years of relevant experience in Digital ASIC or FPGA design
  • Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects through concept development, architectural exploration, design implementation, lab validation, and production release.
  • Extensive experience coding RTL (verilog preferred).
  • Extensive experience using digital simulation tools (Cadence preferred).
  • Extensive experience using static timing analysis tools.
  • Experience designing with the following: PCIe, DDR3/4/5, AXI, ethernet, SPI, SERDES
  • Experience with either AMD or Altera FPGAs and development tools (Vivado/Quartus), preferably both.
  • Experience using digital design quality tools e.g. Lint, CDC.
  • Experience with bug tracking tools
  • Experience with source control systems and continuous integration.
  • Familiarity with digital verification tools and methodologies (preferably UVM).
  • Experience with project scheduling tools
  • Excellent presentation and communication skills.


Additional Desired Skills:
  • Experience developing hardware for automated test equipment
  • Experience as a first level manager of an engineering team.
  • Experience with FPGA Transceiver based designs
  • Experience with DRAM and Flash Memory interfaces
  • Experience with Linux and Windows operating systems
  • Familiarity with ATE instrumentation


Compensation: The base salary range for this role is $171,000-$273,600. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance.

Benefits: Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here to see details.

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About Teradyne

Teradyne, Inc. is a leading supplier of automation equipment for test and industrial applications. Teradyne Automatic Test Equipment (ATE) is used to test semiconductors, wireless products, data storage and complex electronic systems, which serve consumer, communications, industrial and government customers. Industrial Automation products include Collaborative Robots used by global manufacturing and light industrial customers to improve quality and increase manufacturing efficiency. In 2019, Teradyne had revenue of $2.3 billion and today employs 5,500 people worldwide. For more information, visit teradyne.com. Teradyne(R) is a registered trademark of Teradyne, Inc. in the U.S. and other countries.
Learn more about Teradyne
Size
5,900 employees
Market Cap
$13.1 billion
Industry
Net Income
$784.1 million
Founded
1960
5 Year Trend
+16.1%
Revenue
$3.1 billion
NASDAQ

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