Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
Key job responsibilities
Create FPGA solutions to support LEO's Optical inter satellite Link system. This is a unique opportunity to define a new system with few legacy constraints. The FPGA design engineer will work with systems teams to define/develop/implement/test/release FPGA based solutions to enable LEO. This will focus on creating digital designs using the latest generations of FPGA technologies and tools.
In this role you will:
Have ownership of one or more FPGA bitstreams. - Create and release FPGAs through the development phases of uArchitecture-RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon Validation
Collaborate with system architects to define and design/implement/test/release/support functions targeted to FPGA technology
Collaborate with system architects and design engineers to implement digital logic functions in FPGAs
Collaborate with system architects and design engineers to implement digital logic functions in FPGA prototypes to validate/tradeoff architecture & design alternatives
Collaborate with systems architects, HW engineering design teams & FW/SW design teams to bring up and test the system solutions.
Drive trade-off analysis to benefit customer experience and optimization of target technology resources for cost/size/power/performance/features
BASIC QUALIFICATIONS
- Bachelor's degree in electrical engineering or equivalent
- Experience in writing test scripts (Python preferred) to validate FPGA images in HW
- 3+ years of experience with ASIC/FPGA design and verification tools
- 3+ years of experience in ASIC/FPGA design verification using System Verilog, UVM
- Experience with Xilinx/AMD (or Altera) FPGAs
- Experience with uArchitecture, RTL coding, lint checks, CDC, RDC, FPGA optimization for timing & power, simulation, and validation
PREFERRED QUALIFICATIONS
- 5+ years of full RTL development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience
- Experience developing python tests for HW testing
- Designs, optimizes, and implement digital logic functions in control/communication and data acquisition systems
- Deep understanding of logic elements, memory blocks, DSP slices, and I/O capabilities
- Familiarity with AXI4 and AXI Streaming interfaces
- Proven track record of successfully taking FPGA/ASIC designs from development through production and deployment
- Experienced in integrating HDL simulation and hardware-in-the-loop (HIL) testing into CI/CD pipelines, ensuring automated regression testing and timing analysis validation for every code commit.
The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.
USA, WA, Redmond - 117,300.00 - 160,000.00 USD annually
