FEA Packaging Engineer

Cspeed

$130K — $155K *
Technical Services
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • MS or PhD in Mechanical Engineering, Materials Science, Engineering Mechanics, or equivalent
  • 6+ years of experience in finite element analysis for semiconductor packaging or electronic systems
  • Expert proficiency in a commercial FEA or CFD tool with working knowledge of a second tool
  • Strong fundamentals in FEA including meshing, boundary conditions, and convergence
  • Demonstrated ability to correlate simulations with physical measurements
  • Experience with advanced packaging techniques such as flip chip and heterogeneous integration

Responsibilities

  • Build and maintain thermal models for the optical engine package
  • Resolve temperature fields across photonic ICs for design accuracy
  • Predict assembly warpage and manage flatness and coplanarity parameters
  • Analyze stress interactions and ensure compliance with JEDEC standards
  • Define modeling standards and ensure auditable results
  • Lead correlation efforts with measured data and revise methodologies accordingly
  • Provide support during architecture definition and engage with suppliers

Benefits

  • Comprehensive health benefits including medical, dental, and vision
  • Generous retirement savings plan with employer matching
  • Flexible work hours and opportunities for remote work
  • Professional development support including training and workshops
  • Collaborative and innovative work culture that encourages idea sharing
Full Job Description
The Role

This position performs finite element analysis for CspeedIO optical engine packages across both thermal and structural domains. It is scoped for a strong FEA engineer: demonstrated depth in either thermal or mechanical analysis is expected, and the ability to work competently in the other is required.

The analysis supports package architecture decisions and qualification. Temperature governs optical wavelength and channel uniformity. Deformation and interconnect stress govern assembly yield, reliability, and optical coupling, since warpage displaces optical facets. Both sets of results terminate in the same design decisions, which is why the scope is held in one role.

Correlation against measured hardware is a standing expectation. Results are used for design sign-off, so assumptions must be documented and defensible.
Responsibilities

Thermal analysis
  • Build and maintain thermal models spanning die, package, interface materials, lid, and cold plate, and establish cooling boundary conditions and their validity limits.
  • Resolve the temperature field across the photonic IC to the resolution photonic design requires, and define the heat extraction path and interface material selection for high-flux die within the assembly.

Structural analysis
  • Predict warpage through the assembly process, and own the flatness, coplanarity, and facet planarity budgets that assembly and optical coupling depend on.
  • Analyze bump and interconnect stress, chip-package interaction, and fatigue life, supporting qualification against JEDEC or equivalent methodology.

Methodology and correlation
  • Define modeling standards and document assumptions such that results are auditable.
  • Lead correlation against measured temperature, warpage, cross-section, and reliability data, and revise methodology accordingly.

Design and supplier support
  • Provide requirements, constraints, and sign-off criteria during architecture definition rather than after design freeze.
  • Engage substrate suppliers, OSATs, and cooling and material vendors on process assumptions and measured data.
Required Qualifications
  • MS or PhD in Mechanical Engineering, Materials Science, Engineering Mechanics, or equivalent practical background.
  • 6+ years of finite element analysis for semiconductor packaging or electronic systems, including one product carried from architecture through hardware correlation.
  • Expert proficiency in one commercial FEA or CFD tool and working proficiency in a second covering the other domain - for example Ansys Mechanical or Abaqus alongside Icepak, Fluent, Flotherm, or Celsius.
  • Sound FEA fundamentals: meshing judgment, boundary condition selection, convergence, and the ability to defend a model rather than only to run one.
  • Demonstrated correlation of simulation against physical measurement, and the judgment to distinguish a modeling error from a process excursion.
  • Experience with advanced packaging construction: flip chip, 2.5D/3D, interposers, and heterogeneous integration.
Preferred Qualifications
  • Depth in nonlinear and time-dependent material behavior: creep, viscoplasticity, viscoelasticity, and fatigue.
  • Silicon photonics or optoelectronic packaging, including thermo-optic sensitivity or warpage as an optical alignment constraint.
  • Coupled thermal-structural workflows, including transfer of a computed temperature field into a structural model.
  • Direct-to-chip liquid cooling, or chip-package interaction and low-k dielectric stress.
  • Scripting for model automation and parametric studies, and design of experiments methodology.
Scope and Impact

This position provides the physics basis for package architecture decisions and qualification.

Similar Jobs

More Jobs at Cspeed

More Technical Services Jobs

Find similar FEA Packaging Engineer jobs: