Engineering Program Manager, RISCV

Tenstorrent$100K — $500K *
Consumer Technology
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Experience in CPU, SoC, or silicon development.
  • Strong leadership in cross-functional team alignment.
  • Proven skills in managing high-performance hardware programs.
  • Effective communicator with technical and executive teams.
  • Experience with Functional Safety (FuSa), especially ISO 26262.

Responsibilities

  • Manage the full lifecycle of CPU program from specification to post-silicon debug.
  • Define project scope, schedule, and resource allocation.
  • Lead execution across architecture, design, verification, and DFT teams.
  • Drive risk management and milestone delivery.
  • Engage with stakeholders to set objectives and align resources.

Benefits

  • Hybrid work model based in Austin, TX or Santa Clara, CA.
  • Opportunities to partner with top engineers on real-time design challenges.
  • Involvement in high-impact decision-making processes.
  • Exposure to cutting-edge RISC-V CPU IP development.
Full Job Description
We're looking for a driven Engineering Program Manager-or a hands-on technical lead ready to step into program management-to help lead the charge on our RISC-V CPU team. In this role, you'll be at the center of the action, working across architecture, design, verification, physical design, and DFT to drive the full lifecycle of a high-performance CPU-from spec to tapeout to post-silicon debug. You'll partner with key stakeholders to define bold objectives, lock in milestones, and align the resources needed to bring next-gen compute to life. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are • A technically strong leader with experience in CPU, SoC, or silicon development. • Skilled in aligning cross-functional teams to deliver complex, high-performance hardware programs. • Proactive problem solver who thrives in dynamic, fast-paced environments. • A clear communicator who can engage engineers and executives alike. What We Need • Ownership of full-cycle CPU program management-from spec to tapeout and post-silicon debug. • Ability to define scope, schedule, and resources, and lead execution across architecture, design, verification, and DFT teams. • Proven experience driving silicon development, managing risk, and delivering milestones. • Experience with Functional Safety (FuSa) standards and implementation, especially ISO 26262 and an understanding of automotive industry requirements and standards for hardware development is highly desirable. What You Will Learn • How to lead the delivery of cutting-edge RISC-V CPU IP at scale, both internally and for external customers. • Partnering with top engineers to resolve real-time design challenges, drive schedule trade-offs, and push forward high-impact decisions. • Leading project reviews and reporting to senior leadership on metrics, risks, and mitigation plans. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits.

About Tenstorrent

Tenstorrent is a semiconductor company that designs and develops computer processors for artificial intelligence and machine learning applications. The company's processors are designed to be energy-efficient and scalable, and are used by a range of businesses, from small startups to large enterprises. Tenstorrent was founded in 2016 and is headquartered in Toronto, Ontario.
Learn more about Tenstorrent
Size
51 employees
Industry
Founded
2016

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