Physical Design Engineer:Location: San Jose (on-site)
We are seeking a collaborative Physical Design Engineer to join our high-performance ASIC/SoC team. In this role, you will contribute to the development of next-generation electro-optical engines and complex mixed-signal designs. You will work alongside technical leads to transform RTL into silicon-ready GDS, gaining exposure to leading-edge process nodes and advanced packaging technologies.
This is a growth-oriented role designed for an engineer with a strong foundation in VLSI who is eager to master the complete physical design flow, from synthesis to signoff.
Essential Functions- Block-Level Implementation: Execute the full physical design flow (RTL2GDS) for digital and mixed-signal blocks, including floorplanning, power planning, placement, and routing.
- Timing Closure: Perform Static Timing Analysis (STA) to identify setup/hold violations and implement ECOs to achieve timing convergence.
- Clock Tree Synthesis (CTS): Analyze clock structures and assist in optimizing clock distribution for skew and latency.
- Physical Verification: Run and debug DRC, LVS, and Antenna checks using industry-standard verification tools to ensure manufacturing compliance.
- Power Optimization: Participate in power optimization, including clock gating, power domain, and IR drop analysis.
- Automation: Develop and maintain Tcl/Python scripts to automate standard design tasks and improve flow efficiency.
- Cross-Functional Collaboration: Partner with the RTL design and Custom Layout teams to resolve integration issues and ensure clean hand-offs.
Basic Qualifications- Bachelor's degree in Electrical/Computer Engineering (or related field) with 2+ years of industry experience in physical design OR Master's degree in Electrical/Computer Engineering (or related field) with 0-2 years of industry experience.
- Strong understanding of digital logic design and CMOS device physics.
- Familiarity with the ASIC design cycle, including Synthesis, P&R, STA, and Signoff.
- Hands-on experience (via work or academic projects) with industry-standard P&R tools (e.g., Cadence Innovus/Encounter, Synopsys ICC2/Fusion Compiler).
- Proficiency in scripting languages (Tcl, Python, or Perl) for design automation and data parsing.
- Comfortable working in a Linux/Unix environment.
Preferred Qualifications- Experience or coursework in Advanced Process Nodes (7nm, 5nm, or smaller).
- Prior internship or co-op experience in a Physical Design or Hardware Engineering role.
- Familiarity with physical verification tools such as Mentor Calibre or Synopsys IC Validator.
- Understanding of low-power design standards (UPF/CPF).
- Knowledge of timing constraints (SDC), or signal integrity analysis.
- Experience with version control systems (e.g., Git, Perforce, Subversion).
Salary range: $120,000 - $160,000
NOTE TO RECRUITERS:
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don't send candidates to Ayar Labs, and do not contact our managers.
