Emulation Engineer

MatX

$250K — $500K+*
Information Technology
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • 5-7 years experience in SoC emulation or system-level validation.
  • Hands-on expertise with commercial emulation platforms like Cadence Palladium.
  • Proficiency in Verilog/SystemVerilog with debugging skills.
  • Strong software skills in Python and knowledge of C/C++, Rust, or Tcl.
  • Experience in developing tools and infrastructure beyond running existing flows.
  • Capable of cross-functional collaboration across teams.

Responsibilities

  • Define and implement emulation strategies for complex SoCs.
  • Debug large-scale models using platforms like Cadence Palladium.
  • Integrate external components and develop custom transactors as necessary.
  • Create HW/SW co-emulation flows with hardware and software tests.
  • Build reusable emulation components, focusing on efficiency and usability.
  • Automate regression triage and improve debug processes.
  • Develop practical AI-based tools for engineering tasks and workflows.

Benefits

  • 4 weeks PTO plus 12 holidays and 3 weeks remote work.
  • Company-subsidized medical, dental, and vision insurance.
  • Retirement plans with 5% company contribution to 401K.
  • $1500 annual professional development budget.
  • Onsite team meals and full reimbursement for commuting expenses.
  • Mental health benefits fully covered via SpringHealth.
  • Generous parental leave policies and reproductive health support.
Full Job Description
MatX is seeking Emulation engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. We're hiring a Senior/Staff Emulation Engineer to build the infrastructure, flows, and debug methodology behind our advanced connectivity SoCs. The role sits in the Emulation team, but the impact is broader: you'll create reusable flows that span emulation, SoC simulation, firmware/software bring-up, and post-silicon validation. We're looking for a multi-disciplinary engineer with an out-of-the-box, can-do mindset - someone who sees a gap and builds the bridge, comfortable moving between RTL, software, tooling, system debug, and vendor flows. You don't need to be an expert in every area listed below. You do need a reuse-first mindset, strong software instincts, and the ability to learn quickly across boundaries. What You'll Do Here - Define and execute emulation strategy and test plans for complex connectivity SoCs. - Bring up and debug large-scale models on commercial emulation platforms such as Cadence Palladium, Zebu or Veloce. - Integrate external components such as SpeedBridge and VirtualBridge adapters, Accelerated VIP, and memory models - for PCIe, HBM4, Ethernet, AXI/AMBA, JTAG, and (Q)SPI. And build custom transactors where needed. - Develop HW/SW co-emulation and co-simulation flows using RTL, software/reference models (Rust, C/C++, SystemC), firmware, and software tests. - Build reusable transactors, agents, stubs, bridges, checkers, and acceleration flows - including developing new transactors and agents from scratch when off-the-shelf options don't fit. - Drive emulation speed-ups and resource utilization - compile-time reduction, partitioning, clocking strategy, regression scheduling, multi-user capacity, and waveform/trace management. - Build automation for regression triage, debug, model usability, and engineering productivity. - Go beyond prompting with AI - build practical LLM-based tooling for log analysis, waveform triage, debug assistance, and flow generation, including custom skills, agents, rules, and workflows that fit our engineering stack. - Collaborate with architecture, RTL, DV, SoC, firmware, driver, kernel, validation, and EDA/vendor teams. Who You Are - Strong hands-on experience with SoC emulation or system-level validation. - Experience with at least one commercial emulation platform, such as Palladium. - Working Verilog/SystemVerilog and waveform-debug skills - enough to develop a custom transactor or agent when needed (with or without AI assistance). Deep RTL design expertise is not required. - Strong software and automation skills - Python plus one or more of C, C++, Rust, Tcl, or shell. - Demonstrated ability to build tools and infrastructure, not just run existing flows. - Strong system-level debug instincts spanning RTL, firmware, and software. - Ability to work independently and across functional and team boundaries. Bonus Points If You Have - UVM or hybrid SoC testbench development. - Integrating cycle-accurate, software, or reference models into emulation/DV flows. - Rust in verification or emulation flows (or strong interest in adopting it). - Bazel or large-scale build/regression systems. - Reusable stimulus across simulation, emulation, and post-silicon. - AI/LLMs used to build real engineering tools - debug, triage, flow generation - beyond chat prompting. - Connectivity SoCs, PCIe/CXL, Ethernet, DMA, HBM/memory subsystems, chiplets, or interconnect fabrics. - Firmware or driver bring-up on emulation platforms. - Scaling emulation or verification infrastructure across multiple projects or product lines. Compensation The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation. - Early Career - $160,000 - $275,000 + equity - Mid Career - $175,000 - $400,000 + equity - Senior Career - $250,000 - $600,000 + equity What We Offer - Time off: 4 weeks PTO (accrued) + 12 company Holidays + up to 3 weeks remote work - Health: Company-subsidized Medical (Kaiser or Anthem) for employees & dependents, Guardian Dental and Vision insurances for employee & dependents, and life insurance (employee only), plus HSA and FSA offerings via Lively. - Financial Wellbeing: Choose from Roth IRA/ 401K (or both) retirement plans with up to 5% company contribution to 401K (even if you don't contribute). Also, 100% company-paid life insurance (up to $300K) and long-term disability insurances. - Professional Development: $1500 Professional Development Budget (per year) - Team Meals: MatX provides onsite team lunch & dinner Monday - Friday, with your choice of ordering via WeBox, Specialty's or via our reimbursement system - Commute on Us: Commute on our company Uber account, or reimburse your train rides. Either way, we pay 100% for your daily commute. - MatX E[x]tras: $50/mo to use on the perk you value most - Cell & Internet Reimbursement: $35/mo for cellular and $40/mo for wifi - Mental Wellbeing: 100% paid mental health benefit via SpringHealth and Guardian EAP. - Support to Parents: Up to 12 weeks paid parental leave regardless of path to parenthood, 10 weeks pregnancy disability leave, flexible return-to-work hours, and Benepass reproductive health & parental benefit. - AI Resources: Up to $20K/month plus a dedicated internal AI Tooling Team to support your productivity All candidates must be authorized to work in the United States and work from our offices in Mountain View Tuesdays-Thursdays.

Similar Jobs

More Jobs at MatX

  • Controller
    $220K — $300K *
    Mountain View, CA 94040 (Santa Clara County)
    Manufacturing & Automotive
    In-Person
  • Silicon Validation Engineer
    $160K — $500K+*
    Mountain View, CA 94040 (Santa Clara County)
    Telecommunications & Hardware
    In-Person
  • Power Architect
    $120K — $500K+*
    Mountain View, CA 94040 (Santa Clara County)
    Enterprise Technology
    In-Person
  • Lead Software Engineer, Kernels
    $250K — $500K+*
    Mountain View, CA 94040 (Santa Clara County)
    Enterprise Technology
    In-Person
  • AI Silicon Architect
    $120K — $500K+*
    Mountain View, CA 94040 (Santa Clara County)
    Enterprise Technology
    In-Person

More Information Technology Jobs

Find similar Emulation Engineer jobs: