Job Details:Job Description: Physical Design and Implementation Lead, Memory PHY IP (DDR/LPDDR)
Intel is seeking an experienced Senior Director of Engineering to lead the Physical Design organization responsible for delivering best-in-class DDR and LPDDR Memory PHY IPs for Intel's Client, Datacenter, and Foundry/ASIC products.
The successful candidate will lead a global team of more than 50 engineers across the United States, India, and Malaysia, consisting of both direct reports and matrixed resources. This leader will drive end-to-end physical implementation, execution excellence, methodology development, and technology enablement for multiple generations of high-performance memory PHY solutions spanning leading-edge process technologies including Intel 18A, Intel 14A, and future nodes.
The role requires a combination of deep technical expertise in high-speed PHY design and physical implementation, strong organizational leadership, and proven experience delivering complex silicon at aggressive schedules across multiple product segments.
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Key Responsibilities
Organizational Leadership
Lead and develop a global team of 50+ Physical Design engineers located across multiple geographies.
Manage a mix of direct and matrix reporting relationships while fostering a high-performance, collaborative engineering culture.
Drive organizational growth, talent development, succession planning, and employee engagement.
Establish clear goals, execution strategies, and performance metrics aligned with business objectives.
Technical Leadership
Own end-to-end Physical Design execution for DDR and LPDDR PHY IPs across multiple Intel product lines.
Drive implementation activities including:
o Floorplanning
o Power planning
o Placement and optimization
o Clock distribution
o Timing closure
o Signal integrity
o Power integrity
o Physical verification
o Design signoff
Lead delivery of high-speed PHY implementations targeting industry-leading performance, power, area, and reliability metrics.
Establish and drive best-known methods (BKMs) for advanced-node implementation and signoff.
Program Execution
Drive predictable execution across multiple concurrent programs supporting Client, Datacenter, and ASIC/Foundry products.
Partner closely with Architecture, Circuit Design, RTL Design, Verification, Package, Product Engineering, and Technology Development teams.
Manage schedule, resource allocation, risk mitigation, and milestone delivery.
Ensure successful tape-in and tape-out of complex PHY IPs on aggressive product timelines.
Methodology and Innovation
Champion next-generation Physical Design methodologies, automation, and AI-assisted design flows.
Drive productivity improvements through scalable automation and design reuse strategies.
Lead adoption of advanced implementation techniques required for sub-2nm technologies.
Promote technical innovation, patents, and continuous improvement initiatives.
Stakeholder Engagement
Communicate effectively with senior engineering leaders, product teams, and executive management.
Drive alignment across geographically distributed organizations and external partners.
Present technical status, risks, and strategic recommendations to executive leadership.
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Qualifications:Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or related discipline with 15+ years of industry experience; Master's or PhD preferred.
18+ years of semiconductor design experience with significant leadership responsibility.
Proven experience leading large-scale Physical Design organizations.
Demonstrated success delivering high-speed PHY, SerDes, DDR, LPDDR, or other complex mixed-signal IPs into production.
Deep expertise in advanced node implementation including Intel 18A, Intel 14A, 2nm-class technologies, or equivalent leading-edge process nodes.
Extensive experience with:
o Timing closure
o Power optimization
o Signal integrity
o Reliability analysis
o Physical verification
o Design signoff methodologies
Experience managing globally distributed teams across multiple geographic regions.
Excellent communication, organizational, and people leadership skills.
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Preferred Qualifications
Expertise in DDR5, LPDDR5/LPDDR6, HBM, or next-generation memory interfaces.
Strong understanding of PHY architecture and mixed-signal design challenges.
Experience delivering IP across Client, Datacenter, AI Accelerator, and Foundry/ASIC markets.
Knowledge of advanced packaging technologies and system-level integration considerations.
Experience driving AI-enabled design productivity and design automation initiatives.
Proven track record of building high-performing engineering organizations and developing future technical leaders.
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Success Profile
The ideal candidate combines:
Deep technical credibility in high-speed PHY implementation.
Strong leadership experience managing large global teams.
Proven success delivering silicon on leading-edge process technologies.
Exceptional execution discipline and customer focus.
Ability to influence across organizational boundaries and drive results through both direct and matrix structures.
This leader will play a critical role in enabling Intel's next generation Client, Datacenter, AI, and Foundry products through the successful delivery of world-class Memory PHY IP solutions.
Job Type:Experienced Hire
Shift:Shift 1 (United States of America)
Primary Location: US, California, Folsom
Additional Locations:US, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $220,920.00-361,480.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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