As a Digital ATE Test Engineer, you will be a key contributor to the development and execution of high-volume production test solutions for custom modem and communication SoCs powering Amazon Leo's satellite constellation. You will partner closely with DFT, ASIC design, and manufacturing teams to translate design-for-test content into production-ready test programs from initial pattern conversion and silicon bring-up through high-volume manufacturing release.
This role demands deep expertise in digital ATE test methodology for complex modem/communication processors, with a strong emphasis on pattern conversion workflows (STIL/WGL to ATE-native formats), production test program bring-up, high-speed I/O and SERDES characterization and production testing, and tight collaboration with DFT teams to ensure comprehensive fault coverage and test quality. You must be responsive, flexible, and able to succeed within an open, collaborative, cross-functional environment.
Export Control Requirement:
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
Key job responsibilities
- Develop and own production test programs for complex digital/modem SoCs on Teradyne UltraFLEX and Advantest platforms, from initial bring-up through high-volume manufacturing release.
- Lead pattern conversion efforts: translate DFT-generated patterns (STIL/WGL) into tester-executable formats (ATP/PAT), validating coverage and ensuring functional equivalence.
- Partner directly with DFT teams to define test insertion strategy, review pattern quality, resolve coverage gaps, and optimize scan/MBIST/BIST content for ATE execution.
- Develop and execute high-speed I/O and SERDES characterization and production test methodologies, including eye diagram analysis, jitter measurement, BER testing, and TX/RX equalization optimization at 30+ Gbps data rates.
- Run and optimize test vectors on ATE platforms, tuning timing, levels, and equalization parameters to ensure repeatability and yield across process corners, voltage and temperature.
- Define SERDES test limits and guardbands based on characterization data, ensuring production screening captures marginal devices while maintaining yield targets.
- Develop and execute test strategies for on-chip one-time programmable (OTP) memory, including understanding of programming mechanisms, verification methodologies, and common challenges such as bit yield optimization, programming voltage margins, redundancy schemes, and post-programming reliability validation
- Review and provide feedback on load board, socket, and probe card designs-assessing signal integrity, power integrity, and layout best practices for high-speed I/O interfaces.
- Define test limits and guardbands based on characterization data, ensuring production screening captures marginal devices while maintaining yield targets and proactively identify test readiness risks, coverage gaps, and optimization opportunities.
- Support qualification activities including burn-in board design, HTOL, ESD, and reliability testing.
- Conduct failure analysis, drive root-cause resolution, and close test correlation issues across the supply and manufacturing chain.
BASIC QUALIFICATIONS
- Bachelor's degree in Electrical Engineering or a related field
- 5+ years of experience in high-speed digital ATE test engineering, preferably in high-volume manufacturing of communication/modem processors or consumer SoCs.
- Demonstrated experience with production test program bring-up and pattern conversion from DFT deliverables to ATE-native formats.
- Experience with high-speed I/O and SERDES test development, characterization, and production screening on ATE platforms.
- Strong written and verbal communication skills.
- International travel required during release-to-production phases.
PREFERRED QUALIFICATIONS
- Master's degree in Electrical or Communications Engineering or a related field
- 5+ years of experience bringing up test programs from initial characterization through high-volume production
- Test program development and optimization on UltraFLEX or Advantest platforms.
- Direct experience testing digital modem, baseband, or communication processor SoCs on ATE.
- Proven track record of collaborating with DFT teams on test insertion planning, coverage analysis and pattern delivery, bring up and optimization (shmoo).
- High-speed SERDES characterization and production test: eye diagram analysis, jitter decomposition (Rj/Dj), BER/BERT testing, TX pre-emphasis/de-emphasis tuning, RX CTLE/DFE equalization optimization.
- Experience with multi-protocol high-speed I/O testing (PCIe, USB, Ethernet, custom PHY) at data rates of 30+ Gbps.
- Digital test techniques: scan, MBIST, ATPG, loopback.
- JTAG, boundary-scan, and IEEE 1149.x protocols.
The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.
USA, CA, Sunnyvale - 176,600.00 - 247,300.00 USD annually
