Job Details:
Job Description:
The Role and Impact
As a DFT Design Engineer, you will play a pivotal role in shaping Intel's silicon solutions. Your contributions will directly influence the quality and efficiency of Intel's products, ensuring seamless integration of Design for Test (DFT) capabilities in cutting-edge designs. This role offers the opportunity to collaborate with architecture, design, verification, and manufacturing teams, contributing to the creation of industry-leading SoC and IP solutions. Your work will drive innovation, enhance test coverage, and optimize the power, performance, and area of complex designs, enabling Intel's leadership in silicon design and manufacturing.
Key Responsibilities
- Develop logic design and register transfer level (RTL) coding to support DFT features such as SCAN, MBIST, and BSCAN.
- Provide timing closure support and test content generation for manufacturing.
- Collaborate in defining architecture and microarchitecture features for blocks, subsystems, and SoCs under DFT.
- Optimize designs to meet power, performance, area, timing, and test coverage goals while adhering to design integrity standards.
- Write, integrate, and verify RTL and structural code for DFT functionality.
- Drive verification efforts to ensure architecture and microarchitecture specifications are achieved.
- Support IP and SoC integration to ensure high-quality implementation of DFT blocks.
- Develop high-volume manufacturing (HVM) content for rapid bring-up and production on automatic test equipment (ATE).
- Collaborate with post-silicon and manufacturing teams to verify features on silicon and document learnings for continuous improvement.
- Drive high test coverage through structural and IP-specific tests to achieve product quality and defect-per-million (DPM) objectives.
Qualifications:
Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
5+ years of experience in DFT, SoC design, or related semiconductor design areas
Tessent Shell flows and SSN methodology
Hands-on experience with ATPG, scan insertion, and/or MBIST/repair
RTL design experience using hardware description languages such as Verilog, VHDL, or SystemVerilog
Preferred Qualifications
Tessent Fast IO, ISTK, and related methodologies
Exposure to or interest in large ASIC applications in design or test
Familiarity with advanced DFT techniques for low-power and high-performance SoC designs
Understanding of industry standards such as IEEE 1687 (IJTAG), IEEE 1149.1 (JTAG), IEEE 1500 (Core Test), and IEEE 1838
Experience with industry-standard DFT tools such as Siemens EDA (Mentor) Tessent, Synopsys DFT Compiler, or Cadence Modus
Proficiency in scripting languages such as TCL, Perl, or Python for design automation
Knowledge of timing constraints, UPF, and low-power design and test methodologies
Experience working across cross-functional teams or contributing to complex SoC projects
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Texas, Austin
Additional Locations:
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
