Minimum qualifications:- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 3 years of experience in DFT architecture, implementation, Automatic Test Pattern Generation (ATPG), and verification for SoCs.
- Experience with industry-standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT).
Preferred qualifications:- Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Experience in DFT flow, including architecture, IP integration (Test controllers, TAP, MBIST), and interaction with synthesis and verification flows.
- Experience with industry-leading EDA tools for DFT, such as Synopsys (e.g., Design Compiler, DFT Max) or Siemens EDA (e.g., Tessent, TestKompress).
- Experience with silicon process and technology nodes for high speed and low power consumption.
- Experience with various fault models (e.g., Stuck-at, Transition, Cell-Aware, Path Delay, etc.).
About the jobIn this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a DFT Engineer, you will be responsible for defining, implementing and deploying advanced design-for-test (DFT) methodologies including Scan, Memory Built-In Self-Test (MBIST), Joint Test Action Group (JTAG) and iJTAG, for highly complex digital or mixed-signal chips or IPs. You will define DFT architecture, and create DFT flows for complex next generation SoCs in partnership with the Design and Physical Design teams. You will also be responsible for design verification of test logic, test pattern generation and debugging and test coverage issues.
US: $138000 - $197000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities - Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high test quality.
- Insert DFT logic, including scan chains, MBIST, Test Access Port (TAP) controller, Clock Control block, and other DFT IP blocks.
- Insert and hook up MBIST logic including test collar around memories, MBIST controllers, electronic fuse (eFuse) logic and connect to core and TAP interfaces.
- Design Verification of DFT logic and test pattern generation.
- Design and Implement System Level Test strategy.
