Job Title: Design Verification Engineer
City: Santa Clara
State/Province: California
Posting Start Date: 8/6/26
Job Description:
Job Description
Key Responsibilities:Strong understanding of SV and UVM and good debugging skills.Understanding of AMBA protocols.Understand design specs and develop test plans based on functional and architectural requirementsBuild UVM/System Verilog-based verification environments for IP/subsystem/SoC level testingDevelop directed and random testcases, perform coverage analysis, and close functional/code coverageDebug simulation failures and work closely with RTL designers to resolve issuesExecute regression runs, analyze results, and contribute to continuous improvementsIntegrate and run power-aware simulations, low power checks, and work with UPF/CPF as neededCollaborate with DFT/PD/RTL teams and post-silicon validation to ensure design quality across domainsDocument test environments, testplans, and results for internal and external reviews
Mandatory Skills: VLSI HVL Verification.
Experience: 3-5 Years.
The expected compensation for this role ranges from $45,000 to $121,000 .
Final compensation will depend on various factors, including your geographical location, minimum wage obligations, skills, and relevant experience. Based on the position, the role is also eligible for Wipro's standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), other paid and unpaid leave options.
Applicants are advised that employment in some roles may be conditioned on successful completion of a post-offer drug screening, subject to applicable state law.
