Design verification Engineer

Scadea Solutions Inc

$90K — $120K *
Technical Services
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • 5+ years in ASIC/SOC verification experience
  • Expert knowledge and hands-on experience in HVL based verification
  • Ability to work collaboratively with design engineers and architects
  • Experience with git version management tool (nice to have)
  • Familiarity with VCS, Questa CDC, and Verdi tools (nice to have)

Responsibilities

  • Conduct subsystem and SoC level verification
  • Create verification plans for various design blocks
  • Enhance existing test benches as necessary
  • Develop test case suites during RTL and GLS release stages
  • Integrate System Verilog and OVM test bench components
  • Create system-level scenarios for full chip testing
  • Debug complex chip simulations to ensure bug-free outputs
  • Perform code and functional coverage analysis prior to RTL releases

Benefits

  • Opportunity to work with cutting-edge technology
  • Collaborative team environment that enhances skill development
  • Full-time role with potential for long-term career advancement
  • Chance to influence quality assurance in design processes
  • Engagement in various project stages to broaden technical expertise
Full Job Description
Role- Design verification Engineer

Location - Allentown, PA

Duration - Full-time

Visa Status - US Citizen / Green Card

Description:

As a design verification engineer, you will be responsible for understanding expected design functionality, Develop test plans and functional validation tests to verify system will meet design requirements. You will be working closely with design engineers, architects and other team members to ensure high quality test plans and flawless test plan execution.

Minimum Qualifications:
• 5+ years of related industry experience in ASIC/SOC verification
• Must have hands-on experience and expert level knowledge on HVL based verification

Duties:
• Subsystem Level & SoC Level verification
• Verification plan creation for various blocks
• Enhance Test Bench if needed
• Develop the SoC/Subsystem Test case suite in various stages like RTL,GLS releases.
• Integrate System Verilog, OVM Test bench components like Scoreboard, Monitors and Bus Function Models.
• Develop System Level Scenario's for full Chip.
• Debug the complex chip simulations and deliver bug free chip
• Perform Code and functional coverage analysis for Various Subsystems
• Meet Quality requirements before various RTL release stages

Nice to have:
• Working experience of git version management tool
• Working experience on VCS, Questa CDC, Verdi
• Ability to deliver high quality output against deadlines and to
• work effectively in cross-site team environment

Qualifications

Additional Information

Required Skills:

Job Description:

Performs highly complex application programming/systems development and support Performs highly complex configuration of business rules and technical parameters of software products Review business requirements and develop application design documentation Build technical components (Maximo objects, TRM Rules, Java extensions, etc) based on detailed design.

Performs unit testing of components along with completing necessary documentation. Supports product test, user acceptance test, etc as a member of the fix-it team. Employs consistent measurement techniques Include testing in project plans and establish controls to require adherence to test plans Manages the interrelationships among various projects or work objectives

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