Cadence Design Systems

Design Engineer I

Cadence Design Systems$88K — $165K *
Cary, NC 27513In-Person
Information Technology
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • BS degree in a relevant field
  • At least 3 years of hands-on experience in SoC DFT.
  • Strong expertise in SCAN, ATPG, and MBIST methodologies.
  • Proficient in pre-silicon validation and post-silicon debug processes.
  • Exceptional problem-solving and debugging skills.
  • Ability to collaborate effectively in a cross-functional engineering environment.

Responsibilities

  • Define and implement SoC level DFT architecture for large and complex designs.
  • Develop, integrate, and support SCAN, ATPG, MBIST, BSCAN, and iJTAG.
  • Conduct DFT insertion, verification, and coverage analysis at block and SoC levels.
  • Drive pre-silicon DFT sign-off, aiming for DRC closure and coverage targets.
  • Support post-silicon debug, failure analysis, and yield improvement efforts.
  • Collaborate with teams in RTL, verification, physical design, and operations.

Benefits

  • Paid vacation and paid holidays
  • 401(k) plan with employer match
  • Employee stock purchase plan
  • Variety of medical, dental, and vision plan options
  • Additional benefits available.
Full Job Description
We are a small group of individuals designing among the most complex chip in the world getting into the award-winning Cadence Design Systems Palladium platform...

As such we are seeking an experienced DFT engineer which role will span across the full spectrum of the DFT implementation: from architecture definition through silicon testing and debug.

A bonus, this individual will have cross functional teams' interactions not only within our group; but across Cadence and the multiple BU involved in our developments.

Key responsibilities:
  • Define and implement SoC level DFT architecture for large and complex designs.
  • Develop, integrate, and support SCAN, ATPG, MBIST, BSCAN and iJTAG.
  • Perform DFT insertion, verification, and coverage analysis at block and SoC levels.
  • Drive pre-silicon DFT sign-off, including DRC closure and coverage targets.
  • Support post-silicon debug, failure analysis and yield learning.
  • Collaborate with RTL, verification, physical design and operation teams.


Qualifications:
  • BS degree
  • At least 3 years of hands-on experience in SoC DFT.


Must-have skills:
  • Strong expertise in SCAN, ATPG, MBIST.
  • Experience with pre-silicon validation and post-silicon debug.
  • Strong problem solving and debugging skills.
  • Ability to work effectively in a cross-functional engineering environment.


Good-to-have skills:
  • Scripting experience (TCL, Perl, Python or equivalent) for flow automation and analysis.
  • Experience with IP-level DFT integration and reuse.
  • Exposure to low-power DFT considerations and complex clocking architectures.
  • Familiarity with manufacturing test flows and silicon yield improvement.

The annual salary range for California is $88,900 to $165,100. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

About Cadence Design Systems

Cadence Design Systems, Inc. is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.
Learn more about Cadence Design Systems
Size
9,300 employees
Market Cap
$43.9 billion
Industry
Net Income
$590.6 million
Founded
2018
5 Year Trend
+10.5%
Revenue
$2.6 billion
NASDAQ

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