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X Note: By applying to this position you will have an opportunity to share your preferred working location from the following:
San Diego, CA, USA; Mountain View, CA, USA.
Minimum qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 4 years of experience with ARM-based SoC verification, including cache coherency, Network-on-Chip (NoC) interconnects, or high-speed bus protocols.
- Experience with post-silicon debug and diagnosing failures across Process, Voltage, and Temperature (PVT) corners.
- Experience in RTL verification and Gate Level Simulation (GLS) workflows.
Preferred qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with UVM/OVM methodologies and using Python or Perl to automate ARM SoC verification flows.
About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a CPU SoC DV Engineer, you will be responsible for ensuring the functional integrity of CPU subsystems from initial RTL simulation through to final silicon characterization. You will develop robust verification environments, drive GLS, and partner with ATE teams to debug and stabilize high-speed patterns in a production environment.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $138000 - $197000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities - Drive ARM SoC and sub-system level verification, simulation, and debug for CPU RTL and gate-level netlists.
- Lead post-silicon debug efforts to diagnose complex hardware failures and ensure pattern stability in production.
- Translate simulation-based functional sequences into ATE/SLT-ready formats, ensuring high-fidelity pattern conversion through virtual tester environments.
- Execute GLS and timing-annotated (SDF) simulations using industry-standard EDA tools.
- Generate and convert ATE patterns utilizing virtual tester environments to ensure high-fidelity translation from simulation.
