Advanced Micro Devices, Inc

CPU Core Physical Design Methodology Staff Engineer

Advanced Micro Devices, Inc • $120K — $160K *
Austin, TX 78745In-Person
Information Technology
Less than 5 years of experience
Today
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Job Overview by Ladders

Qualifications

  • 5-7 years of experience in physical design and EDA methodologies
  • Expert-level proficiency in physical design tools like Synopsys Fusion Compiler and Cadence Innovus
  • Proficient in scripting languages such as Tcl, Python, and Perl
  • Experience with customization of tool-specific APIs for unique design challenges
  • In-depth knowledge of signoff methodologies and high-frequency CPU design
  • Advanced understanding of physical effects at cutting-edge nodes (7nm/5nm/3nm)
  • MS or PhD in Electrical Engineering, Computer Engineering, or related field, or equivalent experience.

Responsibilities

  • Design and maintain comprehensive physical implementation flows from synthesis to signoff
  • Lead EDA tool optimization, collaborating directly with vendors to enhance tool performance
  • Develop advanced scripting frameworks for automating design processes
  • Analyze and adjust tool settings to achieve optimal PPA targets
  • Refine automated signoff processes to ensure efficient and reliable tape-outs
  • Create and validate complex constraints that align optimization with architectural goals
  • Utilize data analysis techniques to improve design metrics and methodologies.

Benefits

  • Flexible working conditions
  • Access to industry-leading technology and tools
  • Opportunities for continuous learning and professional growth
  • Collaborative team environment with skilled professionals
  • Health and wellness programs.
Full Job Description
THE ROLE

We are seeking a Physical Design Methodology Staff Engineer to serve as the technical backbone of our high-performance core team. In this role, you will move beyond standard implementation to focus on the "how" of physical design. You will own the optimization of our EDA tool-chain, developing and refining the methodologies that enable our CPU cores to hit aggressive PPA (Power, Performance, and Area) targets. You will act as a power-user and flow-architect, bridging the gap between raw EDA tool capabilities and the complex requirements of GHz-class silicon.

THE PERSON

You are an EDA-centric engineer who views the design flow as a system to be tuned, automated, and perfected. You are not just a user of tools; you are an expert in how tool algorithms, constraints, and physical parameters interact to produce optimal silicon. If you are driven by the challenge of reducing turnaround time, improving design predictability, and pushing EDA tools to their absolute limits, you are the ideal candidate for this role.

KEY RESPONSIBILITIES
  • Flow Architecture: Design, implement, and maintain end-to-end physical implementation flows (Synthesis through Signoff) that prioritize scalability, reproducibility, and high QoR.
  • EDA Tool Optimization: Act as the primary interface with EDA vendors to drive tool adoption, evaluate new features, and troubleshoot complex tool-behavior issues.
  • Methodology Development: Develop and deploy advanced scripting frameworks (Tcl/Python) to automate design space exploration, ECO implementation, and multi-corner timing closure.
  • PPA Optimization: Systematically analyze and tune tool settings-including placement density, routing congestion management, and clock tree synthesis (CTS) strategies-to meet aggressive frequency and power targets.
  • Signoff Integration: Build and refine automated signoff loops (STA, IR/EM, Physical Verification) to ensure high-confidence tape-outs with minimal iterations.
  • Constraint Engineering: Develop and validate complex SDC constraints, ensuring that tool-driven optimizations are aligned with architectural intent and physical realities.
  • Data-Driven Analysis: Utilize big-data approaches to analyze design metrics across multiple iterations, identifying trends in tool performance and implementing corrective methodology improvements.

PREFERRED EXPERIENCE

EDA & Methodology Expertise
  • Tool Mastery: Expert-level proficiency in industry-standard physical design platforms (e.g., Synopsys Fusion Compiler/ICC2, Cadence Innovus).
  • Scripting & Automation: Advanced Tcl/Python/Perl skills; proven ability to build custom tool wrappers, automated debug utilities, and flow-management scripts.
  • Flow Customization: Experience in customizing tool-specific APIs to handle unique design challenges, such as custom cell integration or non-standard floorplanning requirements.
  • QoR Tuning: Demonstrated success in "tuning the engine"-adjusting tool-specific switches, constraints, and optimization strategies to resolve timing, power, or congestion bottlenecks.

Technical Depth
  • Advanced Node Implementation: Deep understanding of the physical effects at 7nm/5nm/3nm nodes and how to configure EDA tools to mitigate parasitic, crosstalk, and LDE (Layout Dependent Effect) issues.
  • Signoff Methodology: Mastery of the signoff ecosystem (PrimeTime SI, RedHawk-SC, Voltus, Calibre); experience in building "push-button" signoff flows that minimize manual intervention.
  • Clocking & Power Flows: Expertise in configuring advanced CTS methodologies and power-aware implementation flows (e.g., UPF/CPF-driven design, multi-Vt optimization).
  • Constraint Management: Deep knowledge of MMMC (Multi-Mode Multi-Corner) environments and the ability to manage complex timing exceptions in high-frequency CPU designs.

ACADEMIC CREDENTIALS:
  • MS or PhD in Electrical Engineering, Computer Engineering, or a related field (or equivalent industry experience).

LOCATION:

Austin, TX

This role is not eligible for visa sponsorship.

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Benefits offered are described: AMD benefits at a glance.

About Advanced Micro Devices, Inc

Advanced Micro Devices, Inc. Careers

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Join a team of over 12,000 dedicated professionals at the intersection of technology, industry expertise, and digital innovation. At AMD, you will work on groundbreaking projects that shape the future of computing and graphics. Our collaborative environment encourages networking and the sharing of ideas across teams and disciplines.

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Learn more about Advanced Micro Devices, Inc
Size
15,500 employees
Market Cap
$100.9 billion
Industry
Manufacturing & Automotive
Net Income
$2.4 billion
Founded
1969
5 Year Trend
+30.9%
Revenue
$9.7 billion
NASDAQ
AMD
* Ladders Estimates

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