MS with 8+ years of experience or PhD with 3+ years in relevant fields.
Strong understanding of UVM/OVM and assertion-based verification methods.
Proven track record in building verification infrastructure and test planning.
Expertise in Verilog, System Verilog, and proficiency in scripting languages.
Knowledgeable in MIPI, AMBA protocols, and prominent ISAs like RISC-V or ARM.
Experience verifying designs at RTL and post-P&R gate levels.
Ability to thrive in a startup culture and provide technical leadership.
Responsibilities
Collaborate with engineers to create and implement test plans for SoC verification.
Maintain and enhance automation verification environments for SoC.
Develop reusable testbenches and test cases for different verification levels.
Establish regression strategies and ensure comprehensive function coverage.
Analyze and debug simulation failures in partnership with design engineers.
Assist test teams in post-silicon validation processes.
Mentor junior engineers and persist in driving verification efficiency.
Benefits
Collaborative work environment that fosters mentorship and growth.
Opportunities to work on cutting-edge technology, including AI/ML and high-speed IO.
Dynamic startup culture that encourages innovation and autonomy.
Full Job Description
Job Description
Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification.
Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance.
Develop reusable testbench, constrained-random/directed testcases, and verification associated behavioral module for both of block levels and system levels.
Develop regression strategy, methodology and tools(scripts). Define and measure the function coverage. Close verification holes for design releases and tape-out.
Work with design engineers to debug and identify root causes of simulation failure.
Support test engineers for post-silicon validation.
Mentor and coach team members and junior engineers. Drive verification efficiency.
Qualifications
MS with 8+ years of relevant experience or PhD (with 3+ years of experience) in Electrical Engineering, Computer Engineering, Computer Science or related degree.
In depth knowledge of UVM/OVM, Semiformal Verification, assertion-based verification as well as hardware and software co-verification methodology.
Extensive experience of building verification infrastructure, test planning, coverage closure, testbench and testcases development for function/performance verification.
Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding.
Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC-V/ARM or DSP core.
Experience in verifying designs at both of RTL level and post-P&R gate level.
Ability to work in a startup environment, and to work both independently and as a team player with the ability to provide technical leadership to other members of the engineering team
Experience in one or more of the following areas considered a strong plus:
Working knowledge of AI/ML Computing, GPU, ISP architectures and accelerators
Experience in verifying mix-signal design and interface of digital and analog.
Experience of design verification for high speed IO such as PCIE and DDR.
