About The Role You will join the
System on Chip (SoC) Design Team at SK hynix memory solutions America, a group dedicated to delivering best-in-class controllers for high-performance SSDs. This team spans the full design cycle-from micro-architecture and RTL design to timing closure and tapeout readiness-enabling next-generation enterprise and AI data center storage solutions.
Responsibilities - RTL design (Verilog/SystemVerilog) for IP based on existing module or new specifications.
- Collaborate, create clear documentation and communication with Design Verification, Silicon Validation, and Firmware teams to ensure design quality.
Minimum Qualifications- Education: BS/MS/PhD program in Electrical Engineering, Computer Engineering, or related field.
- Proficiency in logic design and micro-architecture; RTL coding in Verilog and/or SystemVerilog language.
Preferred Qualifications - Advanced Education: Master's or PhD in Electrical Engineering with working experiences.
- Experience or coursework in digital logic design, verification methodologies, and protocols (AMBA, PCIe, NAND, DDR)
- Scripting skills (Python, Perl, TCL) and Linux command-line experiences
- Strong problem-solving and communication skills
- Proficiency in AI tool to generate synthesizable and functional RTL code
COMPENSATION: $110,000/yr - $170,000/yrREGARDING COMPENSATION:SK hynix memory solutions America Inc. offers you the opportunity to apply your skills to exciting projects while working with innovative teams. Our compensation package is complimented by a generous benefits package including medical, dental, vision, life insurance and a company 401(k) match, as well as cafeteria, onsite gym and much more. If you are motivated by technical challenges, we offer a collaborative work environment that encourages career growth.
The salary offered to a selected candidate will be tailored based on several factors, including the location, job grade, relevant knowledge, skills, and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness.
