Job DescriptionKey Responsibilities- Design and development of analog and mixed-signal circuits for 3D NAND Flash memory, supporting array operation, peripheral circuitry, and power delivery.
- Drive top-level integration and verification of analog IP within the NAND chip architecture, including interaction with array-level and peripheral power domains.
- Collaborate closely with layout engineers to address dense routing, coupling noise, IR drop, and electromigration challenges specific to 3D NAND layouts.
- Perform circuit simulations, silicon debug, and post-silicon characterization, with focus on array-induced noise, supply droop, and PVT sensitivity.
- Conduct power integrity and noise analysis for NAND-specific stress conditions, including simultaneous wordline/bitline switching, charge pump loading, and peak current events.
- Leverage post-layout RC extraction to evaluate parasitic impacts on wordline, bitline, and power networks, and correlate with silicon behavior.
- Support chip-level power analysis across NAND operating states, including current profiling, peak power characterization, and margin analysis.
QualificationsMinimum Qualifications- At least 5 years of relevant experience with a bachelor's degree in Electrical Engineering or equivalent; advanced degree is a plus.
- Strong understanding of analog circuit design fundamentals, including matching, noise, stability, power consumption, and layout-dependent effects.
- Proficiency with industry-standard design and simulation tools (e.g., Cadence Virtuoso, Spectre, HSPICE, PrimeSim).
- Experience analyzing post-layout simulation results and resolving power- or noise-related issues.
- Strong problem-solving skills with the ability to work independently and across disciplines.
- Excellent written and verbal communication skills, with proven experience in a collaborative engineering environment.
Preferred Qualifications- Experience with 3D NAND or non-volatile memory design
- Experience correlating simulation results with silicon measurements and Post Si design verification
Additional InformationThe compensation range for this role is $121,280 - $194,100. Actual compensation is influenced by a variety of factors including but not limited to skills, experience, qualifications, and geographic location.
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