Lead the charge in deploying and optimizing Generative AI applications and services, focusing on scalable frameworks and responsible AI practices. Collaborate with cross-functional teams to ensure compliance and infrastructure stability.

Shape the future of networking technology as an ASIC Engineer specializing in Design-for-Test. Drive DFT processes, craft innovative solutions, and collaborate across teams to integrate test logic in advanced silicon designs throughout the development cycle.

Engineer innovative test processes for cutting-edge silicon devices. Collaborate with multi-functional teams to enhance chip design, integration, and validation. Drive advancements in Design-for-Test methodologies throughout the development cycle.

Transform the future of networking as you tackle complex STA challenges, collaborating with cross-functional teams to enhance design quality and validation processes, and drive innovative chip development in this critical engineering role.

Elevate your expertise as you collaborate in developing innovative networking chips, ensuring precise timing constraints through detailed analysis and quality processes while engaging cross-functional teams in a fast-paced environment.