Support the evolution of ECAD library management by enhancing design workflows, ensuring data integrity, and implementing automation solutions. Collaborate with cross-functional teams to drive efficiency and innovative engineering practices.

Empower the development of high-level simulations by translating custom mixed-signal circuit schematics into efficient SystemVerilog behavioral models, ensuring close collaboration with circuit and DV teams for optimal verification and performance.

Optimize performance by translating mixed-signal circuit schematics into efficient SystemVerilog models for simulations, collaborating with circuit and DV teams to ensure accuracy and effectiveness in verification and functionality.

Elevate design processes by ensuring optimal timing closure across SoC design, collaborating with RTL, CAD, and Physical teams to achieve high-quality sign-off and innovate effective solutions for timing analysis and constraints management.

Engineer PCIe driver technology, enhancing performance across diverse products while contributing to innovative system solutions in a collaborative environment that values rapid product iteration.