Renesas is seeking an experienced Staff Verification Engineer. As mixed-mixed signal verification engineer you will be responsible for the verification and modeling of mixed-signal Automotive power management devices, including PMICs, switching regulators, and related analog IP. You will work closely with design, systems, validation, and CAD teams to drive successful development, integration, and sign-off of complex mixed-signal power chips. Key Responsibilities • Design and architect mixed-signal verification environments, including Real Number Model (RNM) and AMS (Analog Mixed Signal) model integration for PMIC designs • Develop and implement comprehensive verification plans and strategies for automotive PMIC products, ensuring compliance with automotive safety standards (ISO 26262, AEC-Q200) • Lead debugging activities for complex analog blocks including switched-mode regulators, Linear Dropout (LDO) regulators, and mixed-signal interfaces • Set up and optimize Gate-Level Simulation (GLS) flows, correlating with RTL simulation results to identify and resolve discrepancies • Conduct in-depth RTL and Gate-Level simulations, analyzing timing, power, and functional correctness across process, voltage, and temperature (PVT) corners • Collaborate closely with cross-functional teams: Design, Application Engineering, ATE (Automatic Test Equipment), and Silicon Validation to ensure seamless verification handoffs • Troubleshoot and debug complex design issues involving interactions between analog and digital domains using simulation and measurement techniques • Drive continuous improvement of verification tools, methodologies, and infrastructure, evaluating emerging verification technologies and AI-based solutions • Create and maintain comprehensive verification documentation, test plans, and coverage metrics Qualifications • MS or PhD in Electrical Engineering, Computer Engineering, or related field • 12+ years of experience in mixed-signal or analog circuit verification • Deep understanding of all aspects of mixed-signal verification environment architecture and implementation • Hands-on experience with Real Number Model (RNM) and AMS (Analog Mixed Signal) model integration • Proficiency in RTL and behavioral simulation tools (e.g., Spectre, Xcelium) • Strong understanding of Gate-Level Simulation (GLS) flows and ability to set up and debug GLS simulations • Proven expertise debugging both analog blocks (switched-mode regulators, LDO, bandgap, reference circuits) and digital RTL • Experience with automotive PMIC or power management IC design and verification • Proficiency in Verilog, SystemVerilog, and/or SPICE-based languages • Solid understanding of verification methodologies: UVM, assertions, coverage-driven verification • Experience interfacing with multiple verification domains: functional, post-silicon, ATE test correlation • Excellent problem-solving and debugging skills with strong analytical mindset • Leadership and mentoring experience Additional Information We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Videos To Watch https://www.youtube.com/watch?v=k-zs4tB6nNc&t=15s