Job Description

As a Staff FPGA Engineer, you will work with a group of talented and dedicated people
to improve and extend Intuitive robotic product lines. You will contribute broadly to the
Future Forward group, with focus on development of innovative electronics at the heart
of Intuitive systems.

As a member of the Future Forward engineering team, you will be involved in
designing, implementing, and testing complex FPGA designs and integrate them into
complete surgical robot solutions and seeing these through human use and product
release.

The successful candidate must excel in a high-energy small, focused team
environment, be able to drive to solutions from rough requirements and methodical
prototype iterations and have a commitment to high product quality that places
patients first.

Quick learning and a desire to understand requirements from a user's and
engineering's perspective are essential to become a valuable system developer. A
strong sense of shared responsibility and shared reward is required, as is the ability to
make work fun and interesting. Supporting you will be a development and
management team that knows and cares about what you are doing and wants you to
succeed.

This position has responsibility for all aspects related to the FPGA design for
electronic board for robotic surgical systems. The Staff FPGA Engineer will:

• Serve as a lead technical designer on project teams to develop new world-class surgical robotic systems and accessories.
• Implement FPGA design using System Verilog in the following areas: video signal processing, DMA, high-speed communications, sensor integration, motor control, and modern embedded computing modules.
• Verify implemented design in simulation and hardware.
• Collaborate with cross-functional teams to Integrate, debug, and support the product before and after launch.
• Write detailed design documentation, including specifications and verification protocols.
• Support the quality and regulatory processes.

Qualifications

Required Skills and Experience

• Expertise in Verilog and SystemVerilog for both synthesis and verification, with a strong command of RTL design principles.
• Extensive experience in FPGA and front-end IC design, including architecture, implementation, and optimization.
• Deep understanding of FPGA architecture, covering design methodologies, timing analysis, verification strategies, and debugging techniques.
• Proficient in FPGA design tools such as Vivado, QuestaSim, and Chipscope, with hands-on experience optimizing workflows.
• Skilled in scripting languages like Python, Tcl, Perl, or Shell for automation and design flow enhancement.
• Experienced with version control systems such as Git and SVN, ensuring efficient collaboration and project management.
• Strong communication, presentation, and technical documentation skills, facilitating seamless collaboration across teams.
• Proficient in C/C++ and MATLAB, leveraging these languages for modeling, simulation, and system-level design.

Required Education and Training

• BSc degree in Electrical Engineering or adjacent technical field with 15 years of experience, or Master's degree with 12 years of experience, or PhD degree with 8 years of experience.

Additional Information

Due to the nature of our business and the role, please note that Intuitive and/or your customer(s) may require that you show current proof of vaccination against certain diseases including COVID-19. Details can vary by role.

This position may be filled at a different job level than listed here depending on
business need and/or on the selected candidate's experience, knowledge and skills.
Compensation will be based primarily on the job level at which the role is filled and the
candidate's qualifications, consistent with applicable law.

We provide market-competitive compensation packages, inclusive of base pay, incentives, benefits, and equity. It would not be typical for someone to be hired at the top end of range for the role, as actual pay will be determined based on several factors, including experience, skills, and qualifications. The target compensation ranges are listed.