Job Title: Staff Engineer, Design Verification Engineering
Job Location: Wilmington, Massachusetts
Job Type: Full Time
Rate of Pay: $171,787 - $209,715 per year
Duties: Develop and execute UVM-based verification environments for block-level and full-chip ASIC/SOC designs. Create and implement verification plans and strategies, including constrained-random and directed test cases. Write and analyze functional coverage, assertions, and metrics to ensure thorough verification and track progress. Integrate and verify third-party and custom IPs/VIPs within subsystem-level UVM environments. Collaborate with design and cross-functional teams to review test plans, resolve issues, and ensure coverage closure. Support post-silicon verification activities, working with evaluation and applications engineering teams. Automate simulation data analysis and model validation using scripting languages and design automation tools.
Partial telecommute benefit (2 days/week work from home).
Requirements: Must have a Master's degree in Computer Science, Computer Engineering, Electrical Engineering, Electronic Engineering, or closely related technical field (willing to accept foreign education equivalent) and four (4) years of experience as a Design Verification Engineer or related occupation performing IC design or validation.
In the alternative, a Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, Electronic Engineering, or closely related technical field (willing to accept foreign education equivalent) and six (6) years of experience as a Design Verification Engineer or related occupation performing IC design or validation.
Must also possess the following (quantitative experience requirements not applicable to this section):
- Demonstrated Expertise ("DE") using metric-driven verification throughout the full lifecycle of design/verification, including verification planning, test bench and test case development using System Verilog and UVM.
- DE learning end application/systems and mapping into smart verification test plans.
- DE translating Design Verification requirements such as test plans into a robust DV environment as well as architecting and analyzing coverage to drive convergence.
- DE using UVM agents, and integrating third-party or custom Verification IPs (VIPs) to develop stimulus sequences and functional checkers within a UVM testbench.
- DE debugging simulations and analyzing waveforms.
Contact: Eligible for employee referral program. Apply online at https://www.analog.com/en/careers.html and Reference Position Number: R264022.
- Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.
- This position qualifies for a discretionary performance-based bonus which is based on personal and company factors.
- This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.
