Role OverviewYou will lead the migration of proven high-speed SerDes and mixed-signal blocks into new process nodes for d-Matrix's IO chiplet, and own the verification and characterization infrastructure the rest of the analog team depends on. Node migration at these data rates is a design problem rather than a mechanical one - this role exists because we'd rather have someone own it properly than see it absorbed in pieces across the team. This is a hands-on role with clear scope and visible impact on schedule, suited to an engineer who takes satisfaction in making a large body of design work correct, measurable, and reusable.
What You Will Do- Own design of existing SerDes and mixed-signal blocks into new process nodes: device mapping, re-sizing, bias/headroom re-budgeting, and re-verification against original specifications.
- Identify where a port stops being a port - blocks whose architecture won't survive the node change - and raise those early with a recommendation.
- Build and maintain the analog verification infrastructure: testbench frameworks, regression setup, corner and Monte Carlo campaigns, and results management the whole team can rely on.
- Run post-layout back-annotated verification and close the loop with layout engineers on parasitic-driven problems.
- Generate and maintain behavioral and Verilog-A models of analog blocks for full-chip verification, keeping them correlated with the transistor-level design.
- Own reliability and design-rule closure for your blocks: electromigration, IR drop, ESD/latch-up compliance, and aging where required.
- Contribute to testboard design and test feature definition, then run silicon characterization - building the bench setup, writing automation, and correlating measured results against simulation.
- Turn characterization results into a feedback loop: document what silicon actually did and make sure the findings reach designers, the next node's port, and product test/reliability teams.
What You Will Bring- BS or MS in Electrical Engineering, with 5+ years of hands-on analog or mixed-signal circuit design experience.
- Demonstrated ownership of analog or mixed-signal blocks through to working silicon, including bench characterization and lab debugging - with the ability to walk through what you were responsible for, what silicon measured, and how you closed the gap between the two.
- Direct experience migrating analog blocks between process nodes, with a realistic account of where that effort actually goes.
- Strong analog verification methodology - corner and Monte Carlo strategy, post-layout back-annotated simulation, and fluency with Cadence Virtuoso/Spectre/ADE - with the discipline to build setups other engineers can use.
- Scripting proficiency in Python, SKILL, TCL, or equivalent, sufficient to automate verification and bench measurement rather than repeat it by hand.
Preferred Qualifications- High-speed SerDes block experience at 25 Gbps or above per lane, in any part of the datapath or clocking subsystem.
- Circuit design experience in FinFET or GAA nodes at 7nm or below.
- Die-to-die interconnect experience - UCIe, BoW, or a proprietary D2D PHY.
- Reliability analysis flows: electromigration, IR drop, aging, and ESD verification.
- Verilog-A and behavioral modeling depth, including model-to-silicon correlation.
- ATE and production test development, or IBIS-AMI model generation.
- Experience building verification or characterization infrastructure that outlived the project it was written for.
