Introduction:We are seeking an experienced Principal Analog Design Engineer to own and drive the architecture and design of high-performance analog/mixed-signal IP used across multiple SoCs. This role will focus on signal chain IP (ADCs, DACs, amplifiers, sensor interfaces) or power management IP (LDOs, DC-DCs, charge pumps, bandgaps).
Essential Responsibilities:- Develop analog and mixed signal IP for products developed by MIPS covering industrial, automotive and other end-equipment. Develop high performance analog and mixed signal IP covering signal chain IPs such as ADC (SAR, pipeline, delta-sigma), DACs, precision amplifiers, clocking, sensor interfaces or develop power management IP such as LDOs, DC-DC converters (buck-boost, buck, boost), bandgap references, charge pumps, power sequencing and monitoring circuits like POR, power good, power glitch etc.
- Strong demonstrated design implementation ability to perform transistor-level design using advanced CMOS technology nodes. Lead schematic design, simulation, and verification across PVT corners. Strong understanding of analog design fundamentals and technology aspects. Understanding and knowledge of design implementation for robustness covering process variation, mismatch, noise and reliability issues for advanced process nodes.
- Cross-collaboration across disciplines working closely with digital, system, layout, and product teams. Strong understanding of system level issues, noise, performance, area trade-offs, reliability considerations. Provide technical leadership during architectural analysis.
- Silicon Execution to support top-level integration, verification and tape-out. Lead silicon bring-up, characterization and bring-up of the IPs designed. Drive continuous improvements and lessons learnt for next-generation IP for re-use and scalability
- Validation and Characterization skills on post-silicon. Ability to define validation and characterization requirements. Understanding spec compliance requirement needs and drive validation teams. Define architecture to meet Design For Test (DFT) requirements and document bring-up, initialization procedures. Drive design for test cost reductions where applicable
- Technical leadership in providing technical guidance and mentorship to other junior engineers working in the team. Establish best practices in analog design methodology and verification. Influence roadmap planning for reusable analog IP platforms
- Stay current with the latest trends in semiconductor design, drive design innovations, providing technical leadership and mentoring within the Hardware engineering team. Participate in internal and external technical forums and lead next generation IP development
Other Responsibilities:Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs
Required Qualifications:- Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.
- Minimum 16+ years of experience in analog mixed signal design in end-end design and delivery of complex analog IP blocks. Proven expertise from concept to silicon is required.
- Deep understanding of CMOS analog design fundamentals, noise analysis, stability and compensation, device mismatch and variation. Experience and proven record of meeting power, performance and area requirements. Strong understanding of low-power design techniques required
- Strong knowledge and understanding of industry-standard EDA tools for design and simulation such as Cadence, Synopsys, Ansys etc. Basic scripting and automation using PERL, Python and expertise in virtuoso and analog simulation environments
- Strong analytical and debugging skills: Ability to identify, assess, and aid in debugging complex problems. Proven silicon bring-up and debugging skills required. Familiarity with lab equipment required
- Excellent communication and documentation skills: Capable of producing clear, comprehensive requirements and architecture and design documentation for both internal and external usage
- Collaborative mindset: Comfortable working in global, cross-disciplinary teams and engaging directly with different disciplines across design
Preferred Qualifications:- Experience in ISO 26262/IEC 61508: Experience in applying the standard throughout the development lifecycle, especially at the semiconductor IP and SoC level
- Strong understanding of analog layout techniques
- Driving innovation and participation in industry level technical events, publishing papers/patents is highly preferrable
Expected Salary Range$171,000.00 - $296,000.00
The exact Salary will be determined based on qualifications, experience and location.
