Education Requirements:

Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 10 years of relevant experience; or Master's degree plus a minimum of 8 years of relevant experience.

Clearance Requirements:

Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

We're looking for a seasoned ASIC Lead Engineer who has been there — not just written RTL, but fought through timing closure under pressure, untangled bus fabric correctness issues, debugged reset sequencing nightmares, and brought complex silicon to tape-out. This is a hands-on technical leadership role for someone who has lived the full ASIC design lifecycle and has the scars to prove it.

If your career has been primarily running P&R tools, this probably isn't the right fit. We need an RTL designer at heart — someone who thinks in architecture and microarchitecture first, and understands the downstream implications of every design decision.

The right candidate is a self-starter who operates with minimal supervision — someone who takes ownership of their domain, drives progress independently, and brings solutions rather than waiting to be directed. You'll be well-integrated within a collaborative team, but we expect you to lead from the front, not follow from behind.

What You'll Do

• Own the architecture — Define the ASIC/FPGA technical approach from concept through silicon, including systempartitioning, microarchitecture, and interface definition
• Drive RTL design — Lead detailed RTL development with a focus on correctness: bus fabric integrity, clock domaincrossings, reset order-of-operations, and design-for-verification
• Close timing — Navigate synthesis, place and route, and static timing analysis with deep understanding of what ittakes to meet timing in advanced process nodes — not just run the tools, but fix the problems
• Lead verification — Serve as the primary point of contact for verification activities; develop and own test andsimulation plans that establish rigorous functional criteria; verify results and drive closure on failures
• Triage and track — Own JIRA triage for the team: reviewing incoming issues, prioritizing work items, and ensuringthe backlog reflects program reality
• Lead code reviews — Conduct and lead RTL code reviews, setting the technical bar and providing actionable, constructive feedback to engineers at all levels
• Support program planning — Contribute to Integrated Master Schedule (IMS) development and Earned Value (EV)reporting; provide accurate technical input on task status, completion criteria, and schedule risk
• Evaluate process flows — High-level design through GDSII, including synthesis, P&R, timing, power analysis, and DFT considerations
• Guide technology selection — Assess foundry technologies, device libraries, IP cores, and EDA tooling to informdesign decisions
• Support proposals and subcontracts — Lead ASIC/FPGA technical approach on large proposals; may serve as book boss on medium proposals; manage technical subcontracts including SOW development, source selection, and work productacceptance
• Grow the team — Mentor junior and mid-level engineers; contribute to the development and improvement oforganizational ASIC/FPGA design processes
• Collaborate broadly — Participate in multi-divisional or multi-company Integrated Product Teams and working groups

What We're Looking For

Experience

• 10–15+ years of ASIC/FPGA design experience, with the majority spent as an RTL designer — not in a purely backend or physical design role
• Proven experience taking designs through full ASIC tape-out, including timing closure, physical verification, andpost-silicon bring-up
• Deep familiarity with FinFET process nodes (7nm, 5nm, or similar) — understanding the nuances of FinFET vs. planartechnology is a meaningful differentiator for this role
• Experience with commercial foundry flows (TSMC, GlobalFoundries, Samsung, or equivalent)
• Demonstrated expertise in:
  • RTL design and microarchitecture definition
  • Bus fabric design and correctness verification
  • Clock domain crossing (CDC) analysis and closure
  • Reset sequencing and order-of-operations validation
  • Timing closure at advanced nodes — not just constraint writing, but root cause analysis and fixing
  • Power analysis and optimization

Skills & Knowledge

• Expert-level understanding of ASIC/FPGA engineering concepts, RTL coding practices, and synthesis flows
• Strong familiarity with industry-standard EDA tools (synthesis, simulation, formal verification, STA)
• Demonstrated ability to operate independently — identifying problems, driving resolution, and keeping work movingwithout requiring day-to-day direction
• Ability to evaluate vendor and foundry capabilities to support product development decisions
• Track record of innovative technical contributions — not just executing to spec, but shaping the approach
• Solid understanding of organizational processes and the ability to apply them pragmatically across a programlifecycle, including schedule management and earned value inputs
• Proficiency in JIRA for issue tracking and backlog management
• Proficiency in Microsoft Office for documentation and communication

Why This RoleYou won't be handed a spec and told to code. You'll help shape what we build, how we build it, and what it takes to get it right. This is a role with real technical latitude, the kind of program impact that shows up in new business, and a team that values engineers who know the difference between running the tools and knowing what the tools are telling you. If you're the kind of engineer who sees a gap and fills it — without being asked — this is the role for you.

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