This is an onsite role based in Santa Clara, CA.

About the job you're considering

As a Physical Design Engineer, you will work on complex digital and mixed-signal designs across advanced process technologies, helping drive designs from implementation through verification and tape-out. This role offers the opportunity to solve challenging physical design problems, collaborate with cross-functional engineering teams, and support next-generation IC product development using industry-leading methodologies and tools.

Your role

As a Physical Design Engineer, you will support the implementation and optimization of advanced-node semiconductor designs. Key responsibilities may include:

• Lead or support physical design activities, including floor planning, placement, clock tree synthesis, routing, and physical-aware synthesis.
• Develop and implement power-grid strategies, high-speed clock constraints, and design specifications to support performance, power, and area goals.
• Perform physical design verification and debug LVS and DRC issues at both chip and block levels.
• Collaborate with design, layout, verification, timing, and methodology teams to address implementation challenges across the design lifecycle.
• Support CDC, static timing analysis, parasitic-aware simulation, and timing closure activities using relevant EDA tools and methodologies.
• Contribute to tape-out readiness, including design signoff, foundry interaction, and alignment with IC product development requirements.
• Evaluate design tradeoffs related to power consumption, area, performance, layout complexity, and technology limitations for advanced process nodes(3nm /5nm/7nm

Your skills and experience

We are looking for candidates with strong physical design expertise and hands-on experience in advanced semiconductor implementation. Ideal qualifications include:

• Must have 10+ years of experience in Physical Design, with hands-on expertise supporting complex digital or mixed-signal IC implementation.
• Strong knowledge of physical design flows, including floor planning, clock tree synthesis, place and route, physical-aware synthesis, and design closure.
• Experience developing power-grid strategies and high-speed clock constraints to support performance, power, and area goals.
• Working knowledge of physical verification methodologies, including LVS and DRC debug at chip and block levels.
• Familiarity with CDC, static timing analysis methodologies, SDF-annotated simulations, and parasitic delay impact.
• Exposure to mixed-signal design environments and the interaction between digital implementation and analog/layout requirements.
• Hands-on experience with tools such as Virtuoso, Calibre, RedHawk, or similar EDA platforms.
• Understanding of design tape-out processes, foundry requirements, and the semiconductor product development supply chain.
• Experience with advanced TSMC process nodes, such as 7nm through 2nm, is highly preferred.

Preferred qualifications

• Experience estimating design and layout effort for digital blocks in advanced-node technologies.
• Strong understanding of power, performance, and area tradeoffs in leading-edge process technologies.
• Prior experience supporting full-chip or block-level tape-out to foundries.
• Ability to work collaboratively across multiple engineering disciplines and communicate technical tradeoffs clearly.

The base compensation range for this role in the posted location is: $82,082 to $193,440

Capgemini provides compensation range information in accordance with applicable national, state, provincial, and local pay transparency laws. The base compensation range listed for this position reflects the minimum and maximum target compensation Capgemini, in good faith, believes it may pay for the role at the time of this posting. This range may be subject to change as permitted by law.

The actual compensation offered to any candidate may fall outside of the posted range and will be determined based on multiple factors legally permitted in the applicable jurisdiction.

These may include, but are not limited to: Geographic location, Education and qualifications, Certifications and licenses, Relevant experience and skills, Seniority and performance, Market and business consideration, Internal pay equity.

It is not typical for candidates to be hired at or near the top of the posted compensation range.

In addition to base salary, this role may be eligible for additional compensation such as variable incentives, bonuses, or commissions, depending on the position and applicable laws.

Capgemini offers a comprehensive, non-negotiable benefits package to all regular, full-time employees. In the U.S. and Canada, available benefits are determined by local policy and eligibility and may include:

• Paid time off based on employee grade (A-F), defined by policy: Vacation: 12-25 days, depending on grade, Company paid holidays, Personal Days, Sick Leave

• Medical, dental, and vision coverage (or provincial healthcare coordination in Canada)
• Retirement savings plans (e.g., 401(k) in the U.S., RRSP in Canada)
• Life and disability insurance
• Employee assistance programs
• Other benefits as provided by local policy and eligibility

Important Notice: Compensation (including bonuses, commissions, or other forms of incentive pay) is not considered earned, vested, or payable until it becomes due under the terms of applicable plans or agreements and is subject to Capgemini's discretion, consistent with applicable laws. The Company reserves the right to amend or withdraw compensation programs at any time, within the limits of applicable legislation.