Be part of Amazon Leo's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies.
In this role you will:
• As the implementation lead you will work with the ASIC design team to develop the chip power intent using UPF
• As the implementation lead you will work with the ASIC design team to validate UPF at RTL and netlist level using industry standard tools
• As the implementation lead you will set up the flow for both logic and physical synthesis flow for various technology nodes.
• Develop implementation methodologies while embracing AI flow.
• Work with the ASIC design and DFT teams to understand the design and create timing constraints.
• Check the RTL design for clean synthesis run, perform STA and LEC on netlist.
• Work with RFIC teams to make sure the top level integration of analog blocks are done properly and correct by construction, including formal connectivity checks.
• Work with P&R teams to ensure a smooth hand off of netlists, ensure the timely execution of the P&R responsibilities by that team.
• Participate in flow reviews of all the blocks with the P&R team to ensure that they achieve the best PPA for all blocks.
• Lead the timing sign-off for the post P&R database.
• Ensure that the chip meets the required DFM criteria by verifying the IR/EM results.
Export Control Requirement:
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
BASIC QUALIFICATIONS
- Bachelor's degree in Electrical Engineering or a related field
- 7+ years of experience in ASIC implementation, i.e., synthesis, STA and working with P&R for deep sub-micron nodes, preferably 16nm or smaller.
- Experience leading or solely developing the methodology and scripts for physical synthesis.
- Proven track record in taping out chips that have gone in to high volume production.
- Familiar with implementing chips that have multiple power islands and power gating.
PREFERRED QUALIFICATIONS
- Master's or Ph.D degree in Electrical / Communications Engineering.
- 10+ years of experience in ASIC implementation.
- Experience in leading physical design.
- Strong exposure to UPF flow for low power design.
- Strong written and verbal skills
- Experience of working in multi-site/multi-team environment
The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.
USA, CA, San Diego - 159,200.00 - 215,300.00 USD annually
USA, CA, Sunnyvale - 183,000.00 - 247,600.00 USD annually
